Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 225

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 115. ESPI State Register (ESPISTATE)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
ESPI State Register
SCKI
R
7
0
TUND—Transmit Underrun
0 = A Transmit Underrun error has not occurred.
1 = A Transmit Underrun error has occurred.
COL—Collision
0 = A multi-Master collision (mode fault) has not occurred.
1 = A multi-Master collision (mode fault) has occurred.
ABT—Slave mode transaction abort
This bit is set if the ESPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the ESPIMODE register. This bit can also be set in SLAVE mode by an SCK
monitor timeout (MMEN = 0, BRGCTL = 1).
0 = A SLAVE mode transaction abort has not occurred.
1 = A SLAVE mode transaction abort has occurred.
ROVR—Receive Overrun
0 = A Receive Overrun error has not occurred.
1 = A Receive Overrun error has occurred.
RDRNE—Receive Data Register Not Empty
0 = Receive Data register is empty.
1 = Receive Data register is not empty.
TFST—Transfer Status
0 = No data transfer is currently in progress.
1 = Data transfer is currently in progress.
SLAS—Slave Select
Reading this bit returns the current value of the SS pin.
0 = The SS pin input is Low.
1 = The SS pin input is High.
The ESPI State register
internal state.
SDI
R
6
0
5
(Table
P R E L I M I N A R Y
115) lets you observe the ESPI clock, data and 
4
F65H
3
ESPISTATE
R
0
Z8 Encore! XP
Enhanced Serial Peripheral Interface
2
Product Specification
1
®
F1680 Series
0
211