Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 168

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
Note:
after the Transmit Shift Register has shifted out the first bit of a character. At this point,
the Transmit Data Register may be written with the next character to send. This provides 7
bit periods of latency to load the Transmit Data Register before the Transmit Shift Register
completes shifting the current character. Writing to the LIN-UART Transmit Data Register
clears the
Receiver Interrupts
The receiver generates an interrupt when any one of the following occurs:
•
In MULTIPROCESSOR mode (
multiprocessor configuration and the most recent address byte
•
•
•
•
LIN-UART Overrun Errors
When an overrun error condition occurs, the LIN-UART prevents overwriting of the valid
data currently in the Receive Data Register. The Break Detect and Overrun status bits are
not displayed until after the valid data has been read.
After the valid data has been read, the
the overrun condition (and Break Detect, if applicable). The
that the Receive Data Register contains a data byte. However, because the overrun error
occurred, this byte may not contain valid data and must be ignored. The
if the overrun is caused by a break condition on the line. After reading the status byte indi-
cating an overrun error, the Receive Data Register must be read again to clear the error bits
in the LIN-UART Status 0 register.
In LIN mode, an Overrun Error is signalled for receive-data overruns as described above
and in the LIN Slave if the BRG Counter overflows during the autobaud sequence (the
ATB
overflow interrupt; however the Receive Data Register must be read to clear the
In this case, software must write a 10B to the
to a Wait for Break state.
A data byte has been received and is available in the LIN-UART Receive Data Register.
This interrupt can be disabled independent of the other receiver interrupt sources via the
RDAIRQ
terrupt occurs once the receive character has been placed in the Receive Data Register.
Software must respond to this received data available condition before the next character
is completely received to avoid an overrun error.
A Break is received.
A Receive Data Overrun or LIN Slave Autobaud Overrun Error is detected.
A Data Framing Error is detected.
A Parity Error is detected (physical layer error in LIN mode).
bit will also be set in this case). There is no data associated with the autobaud 
TDRE
bit (this feature is useful in devices which support DMA). The received data in-
bit to 0.
P R E L I M I N A R Y
MPEN=1
OE
), the receive-data interrupts are dependent on the
bit of the Status 0 register is updated to indicate
LinState
Z8 Encore! XP
field, forcing the LIN slave back
RDA
Product Specification
bit is set to 1 to indicate
BRKD
®
F1680 Series
bit indicates
OE
LIN-UART
bit. 
154