Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 137

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Multi-Channel Timer Interrupts
PS025011-1010
Continuous Compare Operation
PWM Output Operation
Capture Operation
Timer Interrupt
The Multi-Channel Timer provides a single interrupt which has five possible sources.
These sources are the internal timer and the four channel inputs (TInA, TInB, TInC, TInD).
In Continuous Compare operation, a channel interrupt is generated when the channel
compare value matches the timer count. The channel event flag (CHyEF) is set in the
Channel Status1 register (MCTCHS1) and the channel remains enabled. The timer
continues counting according to the programmed mode. If the channel output alternate
function is enabled, the channel output pin (TOutA, B, C, or D) changes state (from Low
to High then back to Low, or High to Low then back to High as determined by the CHPOL
bit) on match.
In PWM Output operation, the timer generates a PWM output signal on the channel output
pin (TOutA, B, C, or D). The channel output toggles whenever the timer count matches
the channel compare value (defined in the MCTCHyH and MCTCHyL) registers. 
In addition, a channel interrupt is generated and the channel event flag is set in the status
register. The timer continues counting according to its programmed mode.
The channel output signal begins with the output value = CHPOL and then transitions to
CHPOL when timer value matches the PWM value. If timer mode is Count Modulo, the
channel output signal returns to output = CHPOL when timer reaches the Reload value
and is reset. If timer mode is Count up/down, channel output signal returns to output =
CHPOL when the timer count matches the PWM value again (when counting down).
In Capture operation, the current timer count is recorded when the selected transition
occurs on TInA, B, C or D. The Capture count value is written to the Channel High and
Low Byte Registers. In addition, a channel interrupt is generated and the channel event
flag (CHyEF) is set in the Channel Status register. The CHPOL bit in the Channel Control
register determines if the Capture occurs on a rising edge or a falling edge of the Channel
Input signal. The timer continues counting according to the programmed mode.
If enabled by TCIEN bit of the MCTCTL0 register, the timer interrupt will be generated
when the timer completes a count cycle. This occurs during transition from counter =
reload register value to counter = 0 in count modulo mode, and occurs during transition
from counter = 1 to counter = 0 in count up/down mode.
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
Multi-Channel Timer
®
F1680 Series
123