Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 202

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 107. ADC Clock Prescale Register (ADCCP)
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Bit Position
[0]
DIV2
[1]
DIV4
[2]
DIV8
[3]
DIV16
[7:4]
Caution:
ADC Clock Prescale Register
7
Value (H)
0
1
0
1
0
1
0
1
0h
The ADC Clock Prescale Register
the ADC. When this register is programmed with
ADC Clock. DIV16 has the highest priority, DIV2 has the lowest priority.
The maximum ADC clock at 2.7 V–3.6 V is 5 MHz. The maximum ADC clock at
1.8 V–2.7 V is 2.5 MHz. Set the Prescale Register correctly according to the different
system clocks. See
6
Description
DIV2
Clock is not divided.
System Clock is divided by 2 for ADC Clock.
DIV4
Clock is not divided.
System Clock is divided by 4 for ADC Clock.
DIV8
Clock is not divided.
System Clock is divided by 8 for ADC Clock.
DIV16
Clock is not divided.
System Clock is divided by 16 for ADC Clock.
Reserved—Must be 0.
Reserved
0
Table 196
5
P R E L I M I N A R Y
on page 349 for details.
(Table
4
F76H
R/W
107) is used to provide a divided system clock to
DIV16
3
0
0h
, the System Clock is used for the
Z8 Encore! XP
DIV8
2
0
Product Specification
Analog-to-Digital Converter
DIV4
1
0
®
F1680 Series
DIV2

0
0

188