Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 245

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

s
PS025011-1010
S
Slave Address
1st Byte
4. The Master detects the Acknowledge and sends the byte of data.
5. The I
6. The software responds by reading the I2CISTAT Register, finding the
7. The master and slave loops through
8. The master sends the
Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from a master to a slave with 10-bit addressing 
is displayed in
Controller operating as a slave in 10-bit addressing mode and receiving data from the bus
master.
Figure 48. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
If software is only able to accept a single byte, it sets the
Register at this time.
Acknowledge depending on the state of the
controller generates the receive data interrupt by setting the
Register.
and reading the I2CDATA Register clearing the
one more data byte it sets the
Acknowledge instruction or runs out of data to send.
cause the I
Register). Because the slave received data from the master, the software takes no
action in response to the STOP interrupt other than reading the I2CISTAT Register to
clear the
mode, as follows:
(a) Initialize the
(b) Optionally set the
(c) Initialize the
(d) Set
mode or MASTER/SLAVE mode with 10-bit addressing.
bits in the I2CMODE Register.
2
W=0
C controller receives the data byte and responds with Acknowledge or Not
IEN
STOP
2
Figure
C controller to assert a STOP interrupt (the
= 1 in the I2CCTL Register. Set
bit in the I2CISTAT Register.
A
MODE
SLA[7:0]
48. The procedure that follows describes the I
Slave Address
STOP
GCE
field in the I2CMODE Register for either SLAVE ONLY
2nd Byte
P R E L I M I N A R Y
bit.
or
bits in the I2CSLVAD Register and the
NAK
RESTART
bit in the I2CCTL Register.
Step 4
A
signal on the bus. Either of these signals can
to
NAK
NAK
Data
Step 6
RDRF
bit in the I2CCTL Register. The I
= 0 in the I
Z8 Encore! XP
until the master detects a Not
bit. If software can accept only
A
STOP
NAK
RDRF
Product Specification
2
I2C Master/Slave Controller
bit = 1 in the I2CISTAT
Data
bit in the I2CCTL
C Control Register.
2
C Master/Slave 
bit in the I2CISTAT
SLA[9:8]
®
RDRF
A/A
F1680 Series
bit = 1
P/S

2
C
231