Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 53

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Stop Mode Recovery
PS025011-1010
External Reset Indicator
On-Chip Debugger Initiated Reset
clock and reset signals, the required reset duration may be as short as three clock periods
and as long as four. A reset pulse three clock cycles in duration might trigger a Reset; a
pulse four cycles in duration always triggers a Reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP F1680 Series devices
remain in the Reset state. If the RESET pin is held Low beyond the System Reset 
timeout, the device exits the Reset state on the system clock rising edge following RESET
pin deassertion. Following a System Reset initiated by the external RESET pin, the
status bit in the RSTSTAT Register is set to 1.
During System Reset or when enabled by the GPIO logic (see
on page 63), the RESET pin functions as an open-drain (active Low) reset mode indicator
in addition to the input functionality. This Reset output feature allows a Z8 Encore! XP
F1680 Series device to reset other components to which it is connected, even if that reset
is caused by internal sources such as POR, VBO, or WDT events.
After an internal Reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in
A POR can be initiated using the OCD by setting the
The OCD block is not reset, but the rest of the chip goes through a normal System Reset.
The
POR
STOP mode is entered by execution of a STOP instruction by the eZ8 CPU. For detailed
STOP mode information, see
Recovery, the CPU is held in reset for 4 IPO cycles.
Stop Mode Recovery does not affect On-chip registers other than the Reset Status
(RSTSTAT) register and the Oscillator Control register (OSCCTL). After any Stop Mode
Recovery, the IPO is enabled and selected as the system clock. If another system clock
source is required or IPO disabling is required, the Stop Mode Recovery code must
reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
The eZ8 CPU fetches the Reset vector at Program Memory addresses
and loads that value into the Program Counter. Program execution begins at the Reset
vector address. Following Stop Mode Recovery, the
RST
bit in the WDT Control Register is set.
Table 8
bit automatically clears during the system reset. Following the System Reset the
on page 34 has elapsed.
P R E L I M I N A R Y
Low-Power Modes
Reset, Stop Mode Recovery, and Low-Voltage
on page 45. During Stop Mode
STOP
RST
Z8 Encore! XP
bit in the OCD Control register.
bit in the Reset Status Register
Port A–E Control Registers
Product Specification
0002H
®
F1680 Series
and
0003H
EXT
39