Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 251

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
I
2
C Control Register
match is achieved on both address bytes. When this bit is set, the
are also valid. This bit clears by reading the I2CISTAT Register.
GCA—General Call Address
This bit is set in SLAVE mode when the General Call Address or Start byte is recognized
(in either 7 or 10 bit SLAVE mode). The
set to enable recognition of the General Call Address and Start byte. This bit clears when
IEN
A General Call Address is distinguished from a Start byte by the value of the RD bit 
(RD = 0 for General Call Address, 1 for Start byte).
RD—Read
This bit indicates the direction of transfer of the data. It is set when the Master is 
reading data from the Slave. This bit matches the least-significant bit of the address byte
after the
clears when IEN = 0 and is updated following the first address byte of each 
transaction.
ARBLST—Arbitration Lost
This bit is set when the I
(outputs a 1 on SDA and receives a 0 on SDA). The ARBLST bit clears when the
I2CISTAT Register is read.
SPRS—
This bit is set when the I
RESTART
I2CISTAT Register is read. Read the
whether the interrupt was caused by a
NCKI—NAK Interrupt
In MASTER mode, this bit is set when a Not Acknowledge condition is received or sent
and neither the
cleared by setting the
In SLAVE mode, this bit is set when a Not Acknowledge condition is received (Master
reading data from Slave), indicating the master is finished reading. A
condition follows. In SLAVE mode this bit clears when the I2CISTAT Register is read.
The I
= 0 and is updated following the first address byte of each SLAVE mode transaction.
2
C Control Register (see
STOP
START
condition during a transaction directed to this slave. This bit clears when the
/
RESTART
START
condition occurs (for both MASTER and SLAVE modes). This bit 
START
nor the
2
2
condition Interrupt
C controller is enabled in MASTER mode and loses arbitration
C controller is enabled in SLAVE mode and detects a
P R E L I M I N A R Y
or
Table
STOP
STOP
bit is active. In MASTER mode, this bit can only be
122) enables and configures I
RSTR
bits. 
STOP
GCE
bit of the I2CSTATE Register to determine
or
bit in the I
RESTART
Z8 Encore! XP
2
C Mode Register must be 
condition.
Product Specification
I2C Master/Slave Controller
RD
2
C operation.
and
STOP
®
GCA
F1680 Series
or
bits 
RESTART
STOP
or
237