Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 101

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
Caution:
Low-Power Modes
When Timer uses peripheral clock and Timer is enabled, any read from TxH or TxL is not
recommended, results may be unpredictable, disable Timer first, then read it. If 
timer work in capture, capture/compare, capture restart or demodulation mode, any read
from TxPWM0H, TxPWM0L, TxPWM1H, TxPWM1L, or TxSTAT must be done after
capture interrupt occurs, or results may be unpredicatable. INPCAP bit of Timer 
Control 0 register is the same as these PWM registers. When Timer uses main clock, 
you can write/read all Timer registers at any time.
Operation in HALT Mode
When the eZ8 CPU enters HALT mode, the timer will continue to operate if enabled. To
minimize current in HALT mode, the timer can be disabled by clearing the TEN control
bit. The noise filter, if enabled, will also continue to operate in HALT mode and rejects
any noise on the timer input pin.
Operation in STOP Mode
When the eZ8 CPU enters STOP mode, the timer continues to operate if enabled and
peripheral clock is chosen as the clock source. In STOP Mode, the timer interrupt (if
enabled) automatically initiates a Stop Mode Recovery and generates an interrupt request.
In the Reset Status Register, the stop bit is set to 1. Also, timer interrupt request bit in
Interrupt Request 0 register is set. Following completion of the Stop Mode Recovery, if
interrupts are enabled, the CPU responds to the interrupt request by fetching the timer
interrupt vector. The noise filter, if enabled, will also continue to operate in STOP Mode
and rejects any noise on the timer input pin.
If system clock is chosen as the clock source, the timer ceases to operate as a 
system clock and is put into STOP Mode. In this case the registers are not reset and 
operation will resume once Stop Mode Recovery occurs.
Power Reduction During Operation
Removal of the
can still read/write registers when the enable bit(s) are taken out.
When timer is operating on a peripheral clock, the timer clock is asynchronous
to the CPU clock. To ensure error-free operation, disable the timer before
modifying its operation (include changing the timer clock source). So any write to the
timer control registers can not be done when timer is enabled and peripheral clock
is used.
TEN
bit will inhibit clocking of the entire timer block. The CPU 
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F1680 Series


Timers

87