Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 147

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 77. Multi-Channel Timer Channel Control Register (MCTCHyCTL
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Multi-Channel Timer Channel-y Control Registers
One-Shot Operation
Continuous Compare Operation
PWM Output Operation
CHEN
R/W
7
0
Each channel has a control register to enable the channel, select the input/output polarity,
enable channel interrupts and select the channel mode of operation.
y = A, B, C, D.
CHEN—Channel Enable.
0 = Channel is disabled.
1 = Channel is enabled.
CHPOL—Channel Input/Output Polarity
Operation of this bit is a function of the current operating method of the channel.
When the channel is disabled, the Channel Output signal is set to the value of this bit.
When the channel is enabled, the Channel Output signal toggles for one system clock on
reaching the Channel Capture/Compare Register value.
When the channel is disabled, the Channel Output signal is set to the value of this bit.
When the channel is enabled, the Channel Output signal toggles (from Low to High or
High to Low) on reaching the Channel Capture/Compare Register value.
0 = Channel Output is forced Low when the channel is disabled. When enabled, the 
1 = Channel Output is forced Low when the channel is disabled. When enabled, the Chan-
02H, 03H, 04H, 05H in Sub-Address Register, accessible through SubRegister 2
Channel Output is forced High on Channel Capture/Compare Register value match
and forced Low on reaching the Timer Reload Register value (modulo mode) or
counting down through the channel Capture/Compare register value 
(count up/down mode).
nel Output is forced High on Channel Capture/Compare Register value match and
forced Low on reaching the Timer Reload Register value (modulo mode) or counting
down through the channel Capture/Compare register value (count up/down mode).
CHPOL
R/W
6
0
CHIEN
R/W
5
0
P R E L I M I N A R Y
CHUE
R/W
4
0
Reserved
R
3
0
Z8 Encore! XP
R/W
)
2
0
Product Specification
CHOP
R/W
Multi-Channel Timer
1
0
®
F1680 Series
R/W
0
0
133