Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 127

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
PWM Dual Output mode
CAPTURE RESTART mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
CAMPARATOR COUNTER mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Triggered ONE-SHOT mode
0 = Timer counting is triggered on the rising edge of the Timer Input signal.
1 = Timer counting is triggered on the falling edge of the Timer Input signal.
DEMODULATION mode 
0 = Timer counting is triggered on the rising edge of the Timer Input signal. 
1 = Timer counting is triggered on the falling edge of the Timer Input signal.
The above functionality applies only if TPOLHI bit in Timer Control 2 register is 0. 
If TPOLHI bit is 1 then timer counting is triggered on any edge of the Timer Input
signal and the current count is captured on both edges. The current count is captured
into PWM0 registers on rising edges and PWM1 registers on falling edges of the
Timer Input signal.
The current count is captured into PWM0 High and Low byte registers 
on subsequent rising edges of the Timer Input signal.
The current count is captured into PWM1 High and Low byte registers 
0 = Timer Output is forced Low (0) and Timer Output Complement is forced 
1 = Timer Output is forced High (1) and Timer Output Complement is forced
on subsequent falling edges of the Timer Input signal.
Output Complement is forced to Low (0).
High (1) when the timer is disabled. When enabled, the Timer Output is 
forced High (1) upon PWM count match and forced Low (0) upon 
Reload. When enabled, the Timer Output Complement is forced Low (0) 
upon PWM count match and forced High (1) upon Reload. The PWMD field 
in Timer Control 0 register is a programmable delay to control the number 
of cycles time delay before the Timer Output and the Timer Output 
Complement is forced to High (1).
Low (0) when the timer is disabled. When enabled, the Timer Output is 
forced Low (0) upon PWM count match and forced High (1) upon 
Reload. When enabled, the Timer Output Complement is forced High (1) 
upon PWM count match and forced Low (0) upon Reload. The PWMD 
field in Timer Control 0 register is a programmable delay to control the 
number of cycles time delay before the Timer Output and the Timer 
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F1680 Series
Timers
113