Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 306

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
OCDCNTR Register
not automatically enable interrupts when using this feature. Interrupts are typically dis-
abled during critical sections of code where interrupts do not occur (such as adjusting the
stack pointer or modifying shared data).
Host software can poll the IDLE bit of the OCDSTAT register to determine if the OCD 
is looping on a BRK instruction. When software wants to stop the CPU on the BRK
instruction on which it is looping, software must not set the DBGMODE bit of the
OCDCTL register. The CPU may have vectored to an interrupt service routine. Instead,
software clears the BRKLP bit. This allows the CPU to finish the interrupt service 
routine it may be in and return to the BRK instruction. When the CPU returns to the 
BRK instruction on which it was previously looping, it automatically sets the DBGMODE
bit and enters DEBUG mode.
The majority of the OCD commands remain disabled when the eZ8 CPU is looping on a
BRK instruction. The eZ8 CPU must be in DEBUG mode before these commands can be
issued.
Breakpoints in Flash Memory
The
byte in Flash memory. To implement a Breakpoint, write
writing the current instruction. To remove a Breakpoint, erase the corresponding page of
Flash memory and reprogram with the original data.
The On-Chip Debugger contains a multipurpose 16-bit Counter Register. It can be used
for the following:
•
•
•
When configured as a counter, the OCDCNTR register starts counting when the On-Chip
Debugger leaves DEBUG mode and stops counting when it enters DEBUG mode again or
when it reaches the maximum count of
resets itself to 0000H when the OCD exits DEBUG mode if it is configured to count clock
cycles between breakpoints.
If the OCDCNTR resister is configured to generate a BRK when it counts down to zero, it
will not be reset when the CPU starts running. The counter will start counting down
toward zero once the On-Chip debugger leaves DEBUG mode. If the On-Chip Debugger
enters DEBUG mode before the OCDCNTR register counts down to zero, the OCDCNTR
will stop counting.
If the OCDCNTR register is configured to generate a BRK when the program counter
matches the OCDCNTR register, the OCDCNTR register will not be reset when the CPU
resumes executing and it will not be decremented when the CPU is running. A BRK will
Count system clock cycles between Breakpoints.
Generate a BRK when it counts down to 0.
Generate a BRK when its value matches the Program Counter.
BRK
instruction is opcode
P R E L I M I N A R Y
00H
, which corresponds to the fully programmed state of a
FFFFH
. The OCDCNTR register automatically
Z8 Encore! XP
00H
to the desired address, over-
Product Specification
®
On-Chip Debugger
F1680 Series
292