R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet
R0K572011S000BE
Specifications of R0K572011S000BE
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R0K572011S000BE Summary of contents
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7201 Group 32 User's Manual: Hardware Renesas ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules ...
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This LSI is an RISC (Reduced Instruction Set Computer) microcomputer that includes a Renesas original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be ...
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Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...
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Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...
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All trademarks and registered trademarks are the property of their respective owners. Page viii of xxviii R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 ...
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Section 1 Overview................................................................................................1 1.1 SH7201 Group Features........................................................................................................ 1 1.2 Product Lineup...................................................................................................................... 8 1.3 Block Diagram...................................................................................................................... 9 1.4 Pin Assignments ................................................................................................................. 10 1.5 Pin Functions ...................................................................................................................... 11 Section 2 CPU......................................................................................................19 2.1 Register Configuration........................................................................................................ 19 2.1.1 General Registers ................................................................................................ 19 2.1.2 Control ...
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Section 3 Floating-Point Unit (FPU)................................................................... 63 3.1 Features............................................................................................................................... 63 3.2 Data Formats....................................................................................................................... 63 3.2.1 Floating-Point Format......................................................................................... 63 3.2.2 Non-Numbers (NaN) .......................................................................................... 65 3.2.3 Denormalized Numbers ...................................................................................... 66 3.3 Register Descriptions.......................................................................................................... 67 3.3.1 Floating-Point Registers ..................................................................................... 67 3.3.2 Floating-Point Status/Control Register ...
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Types of Reset .................................................................................................... 97 5.2.3 Power-On Reset .................................................................................................. 98 5.2.4 Manual Reset .................................................................................................... 100 5.3 Address Errors .................................................................................................................. 101 5.3.1 Address Error Sources ...................................................................................... 101 5.3.2 Address Error Exception Handling ................................................................... 102 5.4 Bus Error........................................................................................................................... 103 5.4.1 Bus ...
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PINT Interrupt Enable Register (PINTER)....................................................... 125 6.3.7 PINT Interrupt Request Register (PIRR) .......................................................... 126 6.3.8 Bank Control Register (IBCR).......................................................................... 127 6.3.9 Bank Number Register (IBNR) ........................................................................ 128 6.3.10 DMA Transfer Request Enable Register 0 (DREQER0) .................................. 129 6.3.11 DMA ...
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Break Data Register (BDR) .............................................................................. 166 7.3.4 Break Data Mask Register (BDMR) ................................................................. 167 7.3.5 Break Bus Cycle Register (BBR)...................................................................... 168 7.3.6 Break Control Register (BRCR) ....................................................................... 170 7.4 Operation .......................................................................................................................... 173 7.4.1 Flow of the User Break Operation ...
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SDRAMCm Control Register (SDCmCNT 1).................................... 211 9.4.4 CSn Mode Register (CSMODn .................................................... 212 9.4.5 CSn Wait Control Register 1 (CS1WCNTn ................................. 215 9.4.6 CSn Wait Control ...
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Section 11 Direct Memory Access Controller (DMAC) ...................................299 11.1 Features............................................................................................................................. 299 11.2 Input/Output Pins.............................................................................................................. 301 11.3 Register Descriptions ........................................................................................................ 302 11.3.1 DMA Current Source Address Register (DMCSADR) .................................... 306 11.3.2 DMA Current Destination Address Register (DMCDADR) ............................ 307 11.3.3 DMA ...
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Reload Function................................................................................................................ 361 11.11 Rotate Function................................................................................................................. 363 11.12 Transfer Speed .................................................................................................................. 364 11.13 Usage Note........................................................................................................................ 366 11.13.1 Note on Making a Transition To Software Standby Mode or Deep Standby Mode ..................................................................................... 366 Section 12 Multi-Function Timer Pulse Unit 2 ...
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Timer Interrupt Skipping Counter (TITCNT)................................................... 448 12.3.29 Timer Buffer Transfer Set Register (TBTER) .................................................. 449 12.3.30 Timer Dead Time Enable Register (TDER)...................................................... 451 12.3.31 Timer Waveform Control Register (TWCR) .................................................... 452 12.3.32 Bus Master Interface ......................................................................................... 453 12.4 Operation ...
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Buffer Operation Setting in Complementary PWM Mode ............................... 558 12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag .............. 559 12.7.16 Overflow Flags in Reset Synchronous PWM Mode ......................................... 560 12.7.17 Contention between Overflow/Underflow and Counter Clearing..................... ...
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Operation with Cascaded Connection............................................................................... 617 13.6.1 16-Bit Counter Mode ........................................................................................ 617 13.6.2 Compare Match Count Mode............................................................................ 617 13.7 Interrupt Sources............................................................................................................... 618 13.7.1 Interrupt Sources............................................................................................... 618 13.7.2 A/D Converter Activation................................................................................. 618 13.8 Usage Notes ...................................................................................................................... 619 13.8.1 Notes on Setting ...
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Register Descriptions........................................................................................................ 641 15.3.1 64-Hz Counter (R64CNT) ................................................................................ 642 15.3.2 Second Counter (RSECCNT) ........................................................................... 643 15.3.3 Minute Counter (RMINCNT) ........................................................................... 644 15.3.4 Hour Counter (RHRCNT)................................................................................. 645 15.3.5 Day of Week Counter (RWKCNT) .................................................................. 646 15.3.6 Date Counter (RDAYCNT) .............................................................................. ...
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Serial Control Register (SCSCR)...................................................................... 680 16.3.7 Serial Status Register (SCFSR)......................................................................... 684 16.3.8 Bit Rate Register (SCBRR)............................................................................... 692 16.3.9 FIFO Control Register (SCFCR) ...................................................................... 700 16.3.10 FIFO Data Count Register (SCFDR) ................................................................ 702 16.3.11 Serial Port Register (SCSPTR) ......................................................................... 703 ...
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Clocked Synchronous Serial Format................................................................. 757 17.4.7 Noise Filter ....................................................................................................... 761 17.4.8 Example of Use................................................................................................. 762 17.5 Interrupt Requests ............................................................................................................. 766 17.6 Bit Synchronous Circuit.................................................................................................... 767 17.7 Usage Note........................................................................................................................ 770 17.7.1 Issuance of Stop Condition and Start Condition (Retransmission)................... 770 ...
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Features............................................................................................................. 812 19.2 Architecture ...................................................................................................................... 813 19.2.1 Block Diagram .................................................................................................. 813 19.2.2 Functions of Each Block ................................................................................... 814 19.2.3 Input/Output Pins .............................................................................................. 815 19.2.4 Memory Map .................................................................................................... 816 19.3 Mailbox............................................................................................................................. 817 19.3.1 Mailbox Structure ............................................................................................. 817 19.3.2 Message Control ...
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Interrupts........................................................................................................... 875 Section 20 A/D Converter (ADC) .....................................................................877 20.1 Features............................................................................................................................. 877 20.2 Input/Output Pins.............................................................................................................. 879 20.3 Register Configuration...................................................................................................... 880 20.3.1 A/D Data Registers (ADDRA to ADDRH) .......................................... 880 20.3.2 A/D Control/Status Register (ADCSR) ............................................................ 882 20.4 ...
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Section 22 I/O Ports ...........................................................................................909 22.1 Port A................................................................................................................................ 909 22.1.1 Register Configuration...................................................................................... 910 22.1.2 Port A Data Registers H and L (PADRH and PADRL).................................... 910 22.1.3 Port A Port Registers H and L (PAPRH and PAPRL) ...................................... 912 22.2 Port ...
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Section 24 On-Chip RAM .................................................................................989 24.1 Features............................................................................................................................. 989 24.2 Usage Notes ...................................................................................................................... 990 24.2.1 Page Conflict .................................................................................................... 990 24.2.2 RAME and RAMWE Bits ................................................................................ 990 Section 25 Power-Down Modes ........................................................................991 25.1 Features............................................................................................................................. 991 25.1.1 Power-Down Modes ......................................................................................... 991 25.2 Register ...
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H-UDI Reset ................................................................................................... 1025 26.4.5 H-UDI Interrupt .............................................................................................. 1025 26.5 Usage Notes .................................................................................................................... 1026 Section 27 Advanced User Debugger II (AUD-II) ..........................................1027 27.1 Features........................................................................................................................... 1027 27.2 Input/Output Pins............................................................................................................ 1027 27.3 RAM Monitor Mode....................................................................................................... 1029 27.3.1 Communication Protocol ................................................................................ 1029 ...
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Usage Note...................................................................................................................... 1153 Appendix ...........................................................................................................1155 A. Pin States ........................................................................................................................ 1155 B. Package Dimensions ....................................................................................................... 1160 Main Revisions for This Edition .......................................................................1161 Index .................................................................................................................1183 Page xxviii of xxviii R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 ...
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SH7201 Group 1.1 SH7201 Group Features This LSI is a single-chip RISC (Reduced Instruction Set Computer) microprocessor that integrates a Renesas original RISC CPU core with peripheral functions required for system configuration. The CPU incorporated in this LSI is the ...
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Section 1 Overview Table 1.1 SH7201 Group Features Item Features • CPU Renesas original SuperH architecture • Compatible with SH-1 and SH-2 at object code level • 32-bit internal data bus • Support of an abundant register-set ⎯ Sixteen 32-bit ...
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SH7201 Group Item Features • Floating-point Unit Floating-point co-processor included • (FPU) Supports single-precision (32-bit) and double-precision (64-bit) • Supports data type and exceptions that conforms to IEEE754 standard • Two rounding modes: Round to nearest and round to zero ...
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Section 1 Overview Item Features • Bus state controller CSC ⎯ Seven-channel chip select controller (CSC) (BSC) ⎯ External devices with their bus sizes of 32, 16 bits can be ⎯ Cycle wait function ⎯ The following features ...
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SH7201 Group Item Features • Direct memory access Eight channels; external request available for four of them • controller (DMAC) Can be activated by software, on-chip modules, or external devices ⎯ Software; 1, internal source; 32, external source; 4 • ...
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Section 1 Overview Item Features • Power-down modes Four power-down modes provided to reduce the current consumption in this LSI ⎯ Sleep mode ⎯ Software standby mode ⎯ Deep standby mode ⎯ Module standby mode • Multi-function timer Maximum 16 ...
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SH7201 Group Item Features • Serial communication Eight channels • interface with FIFO Clock synchronous or asynchronous mode selectable (SCIF) • Simultaneous transmission and reception (full-duplex communication) supported • Dedicated baud rate generator • Separate 16-byte FIFO registers for transmission ...
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Section 1 Overview Item Features • A/D converter (ADC) 10-bit resolution • Eight input channels • A/D conversion request by the external trigger or timer trigger • D/A converter (DAC) 8-bit resolution • Two output channels • User break controller ...
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SH7201 Group 1.3 Block Diagram The block diagram of this LSI is shown in figure 1.1. SH-2A CPU core Instruction cache memory (8 kbytes) Cache controller Bus bridge External On-chip bus I/O Bus state peripheral controller module bus 1 External ...
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Section 1 Overview 1.4 Pin Assignments ASEMD 133 134 MD1 135 MD0 WDTOVF 136 137 PVSS 138 PB0/D0 139 PVCC 140 PB1/D1 141 PB2/D2 142 PB3/D3 143 PB4/D4 144 PB5/D5 145 PB6/D6 146 PB7/D7 147 PB8/D8 148 PB9/D9 149 PB10/D10 ...
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SH7201 Group 1.5 Pin Functions Table 1.3 lists the pin functions. Table 1.3 Pin Functions Classification Symbol Power supply VCCR VSSR VCL VSS PVCC PVSS R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 I/O Name Function I Power supply for Power supply ...
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Section 1 Overview Classification Symbol PLLVCC Power supply PLLVSS Clock EXTAL XTAL CKIO Operating mode MD1, MD0 control MD_CLK1, MD_CLK0 ASEMD RES System control MRES WDTOVF ASEBRKAK ASEBRK* Page 12 of 1190 I/O Name Function I Power supply for Power ...
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SH7201 Group Classification Symbol Interrupts NMI IRQ7 to IRQ0 PINT7 to PINT0 I Address bus A27 to A0 Data bus D31 to D0 CS6 to CS0 Bus control RD WAIT WR0 WR1 WR2 WR3 R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 ...
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Section 1 Overview Classification Symbol BC0 Bus control BC1 BC2 BC3 DQM0 DQM1 DQM2 DQM3 SDCS1, SDCS0 SDRAS SDCAS SDWE SDCKE SDCLK Page 14 of 1190 I/O Name Function O Byte select Selects bits data of ...
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SH7201 Group Classification Symbol DREQ3 to Direct memory access controller DREQ0 (DMAC) DACK3 to DACK0 DACT3 to DACT0 DTEND3 to DTEND0 Multi-function TCLKA, timer pulse unit 2 TCLKB, (MTU2) TCLKC, TCLKD TIOC0A, TIOC0B, TIOC0C, TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, ...
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Section 1 Overview Classification Symbol 8-bit timer (TMR) TMO0, TMO1 TMCI0, TMCI1, TMRI0, TMRI1 Realtime clock RTC_X1 (RTC) RTC_X2 Serial TxD7 to TxD0 communication RxD7 to RxD0 interface with SCK7 to SCK0 FIFO (SCIF bus SCL2 to ...
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SH7201 Group Classification Symbol CTx0, CTx1 Controller area network (RCAN-ET) CRx0, CRx1 A/D converter AN7 to AN0 ADTRG D/A converter DA1, DA0 Analog power AVcc supply AVref AVss I/O ports PA31 to PA0 PB31 to PB0 PC25 to PC22 PC21 ...
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Section 1 Overview Classification Symbol Advanced user AUDATA3 to debugger II AUDATA0 (AUD-II) AUDCK AUDSYNC AUDMD AUDRST UBCTRG User break controller (UBC) Note: * The pin with the pull-up function. Page 18 of 1190 I/O Name Function I/O AUD data ...
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SH7201 Group 2.1 Register Configuration The register set consists of sixteen 32-bit general registers, four 32-bit control registers, and four 32-bit system registers. 2.1.1 General Registers Figure 2.1 shows the general registers. The sixteen 32-bit general registers are numbered R0 ...
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Section 2 CPU 2.1.2 Control Registers The control registers consist of four 32-bit registers: the status register (SR), the global base register (GBR), the vector base register (VBR), and the jump table base register (TBR). The status register indicates instruction ...
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SH7201 Group Initial Value Bit Bit Name — All — All — — I[3:0] 1111 3, 2 — All ...
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Section 2 CPU (2) Global Base Register (GBR) GBR is referenced as the base address in a GBR-referencing MOV instruction. Vector Base Register (VBR) (3) VBR is referenced as the branch destination base address in the event of an exception ...
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SH7201 Group (2) Procedure Register (PR) PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is referenced by a subroutine return instruction (RTS). (3) Program Counter (PC) PC points four bytes ahead ...
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Section 2 CPU 2.2 Data Formats 2.2.1 Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits word (16 bits changed into a longword ...
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SH7201 Group 2.2.3 Immediate Data Format Byte (8-bit) immediate data is located in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the ...
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Section 2 CPU 2.3 Instruction Features 2.3.1 RISC-Type Instruction Set Instructions are RISC type. This section details their functions. (1) 16-Bit Fixed-Length Instructions Basic instructions have a fixed length of 16 bits, improving program code efficiency. (2) 32-Bit Fixed-Length Instructions ...
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SH7201 Group (5) Load-Store Architecture Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. ...
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Section 2 CPU (9) T Bit The T bit in the status register (SR) changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number ...
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SH7201 Group (11) Absolute Address When data is accessed by an absolute address, the absolute address value should be placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the ...
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Section 2 CPU 2.3.2 Addressing Modes Addressing modes and effective address calculation are as follows: Table 2.8 Addressing Modes and Effective Addresses Addressing Mode Instruction Format Register direct Rn Register indirect @Rn Register indirect @Rn+ with post-increment Register indirect @-Rn ...
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SH7201 Group Addressing Mode Instruction Format Register indirect @(disp:4,Rn) with displacement Register indirect @(disp:12,Rn) with displacement Indexed register @(R0,Rn) indirect GBR indirect with @(disp:8,GBR) displacement R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 Effective Address Calculation The effective address is the sum ...
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Section 2 CPU Addressing Mode Instruction Format Indexed GBR @(R0,GBR) indirect TBR duplicate @@ (disp:8,TBR) The effective address is the sum of TBR value indirect with displacement PC indirect with @(disp:8,PC) displacement PC relative disp:8 Page 32 of 1190 Effective ...
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SH7201 Group Addressing Mode Instruction Format PC relative disp:12 Rn Immediate #imm:20 #imm:8 #imm:8 #imm:8 #imm:3 R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 Effective Address Calculation The effective address is the sum of PC value and the value that is obtained ...
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Section 2 CPU 2.3.3 Instruction Format The instruction formats and the meaning of source and destination operands are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: • xxxx: Instruction code ...
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SH7201 Group Instruction Formats m format 15 0 xxxx mmmm xxxx xxxx nm format 15 0 xxxx xxxx nnnn mmmm md format 15 0 xxxx xxxx mmmm dddd nd4 format 15 0 xxxx xxxx nnnn dddd R01UH0026EJ0300 Rev. 3.00 Sep ...
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Section 2 CPU Instruction Formats nmd format 15 0 xxxx nnnn mmmm dddd nmd12 format 32 16 xxxx nnnn mmmm xxxx 15 0 xxxx dddd dddd dddd d format 15 0 xxxx xxxx dddd dddd d12 format 15 0 xxxx ...
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SH7201 Group Instruction Formats ni format 15 0 xxxx nnnn iiii iiii ni3 format 15 0 xxxx xxxx nnnn x iii ni20 format 32 16 xxxx nnnn iiii xxxx 15 0 iiii iiii iiii iiii nid format 32 16 xxxx ...
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Section 2 CPU 2.4 Instruction Set 2.4.1 Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Operation Classification Types Code Data transfer 13 MOV MOVA MOVI20 MOVI20S MOVML MOVMU MOVRT MOVT ...
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SH7201 Group Operation Classification Types Code Arithmetic 26 ADD operations ADDC ADDV CMP/cond Comparison CLIPS CLIPU DIVS DIVU DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULR MULS MULU NEG NEGC SUB SUBC SUBV R01UH0026EJ0300 Rev. 3.00 Sep ...
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Section 2 CPU Operation Classification Types Code 6 AND Logic operations NOT OR TAS TST XOR Shift 12 ROTL ROTR ROTCL ROTCR SHAD SHAL SHAR SHLD SHLL SHLLn SHLR SHLRn Branch BRA BRAF BSR BSRF JMP JSR ...
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SH7201 Group Operation Classification Types Code System control 14 CLRT CLRMAC LDBANK LDC LDS NOP RESBANK Register restoration from register bank RTE SETT SLEEP STBANK STC STS TRAPA Floating-point 19 FABS instructions FADD FCMP FCNVDS FCNVSD FDIV FLDI0 FLDI1 FLDS ...
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Section 2 CPU Operation Classification Types Code Floating-point 19 FSCHG instructions FSQRT FSTS FSUB FTRC FPU-related 2 LDS CPU STS instructions Bit 10 BAND manipulation BCLR BLD BOR BSET BST BXOR BANDNOT Bit NOT AND BORNOT BLDNOT Total: 112 Page ...
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SH7201 Group The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Instruction Instruction Code Indicated in MSB ↔ Indicated by mnemonic. LSB order. Explanation of ...
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Section 2 CPU 2.4.2 Data Transfer Instructions Table 2.11 Data Transfer Instructions Instruction Instruction Code 1110nnnniiiiiiii imm → sign extension → Rn MOV #imm,Rn 1001nnnndddddddd (disp × PC) → sign MOV.W @(disp,PC),Rn 1101nnnndddddddd (disp × PC) ...
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SH7201 Group Instruction Instruction Code 0000nnnnmmmm0110 Rm → (R0 + Rn) MOV.L Rm,@(R0,Rn) 0000nnnnmmmm1100 (R0 + Rm) → MOV.B @(R0,Rm),Rn 0000nnnnmmmm1101 (R0 + Rm) → MOV.W @(R0,Rm),Rn 0000nnnnmmmm1110 (R0 + Rm) → Rn MOV.L @(R0,Rm),Rn 11000000dddddddd R0 → (disp + ...
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Section 2 CPU Instruction Instruction Code 11000111dddddddd disp × → R0 MOVA @(disp,PC),R0 MOVI20 #imm20,Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii MOVI20S #imm20,Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii 0100mmmm11110001 R15-4 → R15, Rm → (R15) MOVML.L Rm,@-R15 0100nnnn11110101 (R15) → R0, R15 + 4 ...
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SH7201 Group Instruction Instruction Code 0000000001101000 ~T → T NOTT 0000nnnn10000011 (Rn) → operand cache PREF @Rn 0110nnnnmmmm1000 Rm → swap lower 2 bytes → SWAP.B Rm,Rn 0110nnnnmmmm1001 Rm → swap upper and lower SWAP.W Rm,Rn 0010nnnnmmmm1101 Middle 32 bits ...
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Section 2 CPU 2.4.3 Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI ...
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SH7201 Group Instruction Instruction Code CLIPS.B Rn 0100nnnn10010001 CLIPS.W Rn 0100nnnn10010101 CLIPU.B Rn 0100nnnn10000001 CLIPU.W Rn 0100nnnn10000101 DIV1 Rm,Rn 0011nnnnmmmm0100 DIV0S Rm,Rn 0010nnnnmmmm0111 DIV0U 0000000000011001 DIVS R0,Rn 0100nnnn10010100 DIVU R0,Rn 0100nnnn10000100 DMULS.L Rm,Rn 0011nnnnmmmm1101 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 ...
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Section 2 CPU Instruction Instruction Code EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULR R0,Rn 0100nnnn10000000 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG Rm,Rn 0110nnnnmmmm1011 NEGC Rm,Rn 0110nnnnmmmm1010 SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV ...
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SH7201 Group 2.4.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Instruction Instruction Code AND Rm,Rn 0010nnnnmmmm1001 AND #imm,R0 11001001iiiiiiii AND.B #imm,@(R0,GBR) 11001101iiiiiiii NOT Rm,Rn 0110nnnnmmmm0111 OR Rm,Rn 0010nnnnmmmm1011 OR #imm,R0 11001011iiiiiiii OR.B #imm,@(R0,GBR) 11001111iiiiiiii TAS.B @Rn 0100nnnn00011011 TST Rm,Rn ...
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Section 2 CPU 2.4.5 Shift Instructions Table 2.14 Shift Instructions Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAD Rm,Rn 0100nnnnmmmm1100 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLD Rm,Rn 0100nnnnmmmm1101 SHLL Rn 0100nnnn00000000 ...
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SH7201 Group 2.4.6 Branch Instructions Table 2.15 Branch Instructions Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR ...
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Section 2 CPU 2.4.7 System Control Instructions Table 2.16 System Control Instructions Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDBANK @Rm,R0 0100mmmm11100101 LDC Rm,SR 0100mmmm00001110 LDC Rm,TBR 0100mmmm01001010 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 ...
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SH7201 Group Instruction Instruction Code STC SR,Rn 0000nnnn00000010 STC TBR,Rn 0000nnnn01001010 STC GBR,Rn 0000nnnn00010010 STC VBR,Rn 0000nnnn00100010 STC.L SR,@-Rn 0100nnnn00000011 STC.L GBR,@-Rn 0100nnnn00010011 STC.L VBR,@-Rn 0100nnnn00100011 STS MACH,Rn 0000nnnn00001010 STS MACL,Rn 0000nnnn00011010 STS PR,Rn 0000nnnn00101010 STS.L MACH,@-Rn 0100nnnn00000010 STS.L MACL,@-Rn ...
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Section 2 CPU 2.4.8 Floating Point Operation Instructions Table 2.17 Floating Point Operation Instructions Instruction Instruction Code FABS FRn 1111nnnn01011101 FABS DRn 1111nnn001011101 FADD FRm, FRn 1111nnnnmmmm0000 FADD DRm, DRn 1111nnn0mmm00000 FCMP/EQ FRm, FRn 1111nnnnmmmm0100 FCMP/EQ DRm, DRn 1111nnn0mmm00100 FCMP/GT ...
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SH7201 Group Instruction Instruction Code FMOV.S @Rm, FRn 1111nnnnmmmm1000 FMOV.D @Rm, DRn 1111nnn0mmmm1000 FMOV.S @(disp12,Rm),FRn 0011nnnnmmmm0001 0111dddddddddddd FMOV.D @(disp12,Rm),DRn 0011nnn0mmmm0001 0111dddddddddddd FMOV.S FRm, @(R0,Rn) 1111nnnnmmmm0111 FMOV.D DRm, @( R0,Rn ) 1111nnnnmmm00111 FMOV.S FRm, @-Rn 1111nnnnmmmm1011 FMOV.D DRm, @-Rn 1111nnnnmmm01011 FMOV.S ...
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Section 2 CPU 2.4.9 FPU-Related CPU Instructions Table 2.18 FPU-Related CPU Instructions Instruction Instruction Code LDS Rm,FPSCR 0100mmmm01101010 LDS Rm,FPUL 0100mmmm01011010 LDS.L @Rm+, FPSCR 0100mmmm01100110 LDS.L @Rm+, FPUL 0100mmmm01010110 STS FPSCR, Rn 0000nnnn01101010 STS FPUL,Rn 0000nnnn01011010 STS.L FPSCR,@-Rn 0100nnnn01100010 STS.L ...
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SH7201 Group 2.4.10 Bit Manipulation Instructions Table 2.19 Bit Manipulation Instructions Instruction BAND.B #imm3,@(disp12,Rn) BANDNOT.B #imm3,@(disp12,Rn) BCLR.B #imm3,@(disp12,Rn) BCLR #imm3,Rn BLD.B #imm3,@(disp12,Rn) BLD #imm3,Rn BLDNOT.B #imm3,@(disp12,Rn) BOR.B #imm3,@(disp12,Rn) BORNOT.B #imm3,@(disp12,Rn) BSET.B #imm3,@(disp12,Rn) BSET #imm3,Rn BST.B #imm3,@(disp12,Rn) BST #imm3,Rn BXOR.B #imm3,@(disp12,Rn) ...
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Section 2 CPU 2.5 Processing States The CPU has four processing states: reset, exception handling, program execution, and power- down. Figure 2.6 shows the transitions between the states. Manual reset from any state Manual reset state Interrupt source or DMA ...
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SH7201 Group (1) Reset State In the reset state, the CPU is reset. There are two kinds of reset, power-on reset and manual reset. Exception Handling State (2) The exception handling state is a transient state that occurs when exception ...
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Section 2 CPU Page 62 of 1190 SH7201 Group R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 ...
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SH7201 Group Section 3 Floating-Point Unit (FPU) 3.1 Features The FPU has the following features. • Conforms to IEEE754 standard • 16 single-precision floating-point registers (can also be referenced as eight double-precision registers) • Two rounding modes: Round to nearest ...
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Section 3 Floating-Point Unit (FPU) The exponent is expressed in biased form, as follows bias The range of unbiased exponent distinguished as follows. E min denormalized number, and E Table 3.1 shows E ...
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SH7201 Group Table 3.2 shows the ranges of the various numbers in hexadecimal notation. Table 3.2 Floating-Point Ranges Type Signaling non-number Quiet non-number Positive infinity Positive normalized number Positive denormalized number Positive zero Negative zero Negative denormalized number Negative normalized ...
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Section 3 Floating-Point Unit (FPU 11111111 sNaN qNaN Figure 3.3 Single-Precision NaN Bit Pattern An sNaN is input in an operation, except copy, FABS, and FNEG, that generates a floating-point value. ...
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SH7201 Group 3.3 Register Descriptions 3.3.1 Floating-Point Registers Figure 3.4 shows the floating-point register configuration. There are sixteen 32-bit floating-point registers FPR0 to FPR15, referenced by specifying FR0 to FR15, DR0/2/4/6/8/10/12/14. The correspondence between FRPn and the reference name is ...
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Section 3 Floating-Point Unit (FPU) 3.3.2 Floating-Point Status/Control Register (FPSCR) FPSCR is a 32-bit register that controls floating-point instructions, sets FPU exceptions, and selects the rounding mode. Bit Initial value R/ ...
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SH7201 Group Initial Value Bit Bit Name Cause All Enable All Flag All 0 1 RM1 0 0 RM0 1 Table 3.3 Bit Allocation for FPU Exception Handling Field ...
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Section 3 Floating-Point Unit (FPU) 3.4 Rounding In a floating-point instruction, rounding is performed when generating the final operation result from the intermediate result. Therefore, the result of combination instructions such as FMAC will differ from the result when using ...
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SH7201 Group 3.5 FPU Exceptions 3.5.1 FPU Exception Sources FPU exceptions may occur on floating-point operation instruction and the exception sources are as follows: • FPU error (E): When FPSCR. and a denormalized number is input (No chance ...
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Section 3 Floating-Point Unit (FPU) These possibilities of each exceptional handling on floating-point operation are shown in the individual instruction descriptions. All exception events that originate in the floating-point operation are assigned as the same FPU exceptional handling event. The ...
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SH7201 Group Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates a CPU clock (Iφ), a peripheral clock (Pφ), and a bus clock (Bφ). The CPG consists of a crystal oscillator, PLL circuits, ...
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Section 4 Clock Pulse Generator (CPG) Figure 4.1 shows a block diagram of the clock pulse generator. CKIO Crystal XTAL oscillator EXTAL MD_CLK1 Clock frequency control circuit MD_CLK0 FRQCR [Legend] FRQCR: Frequency control register STBCR: Standby control register STBCR2: Standby ...
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SH7201 Group The clock pulse generator blocks function as follows: PLL Circuit 1 (1) PLL circuit 1 multiplies the input clock frequency from the CKIO pin The multiplication rate is set by ...
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Section 4 Clock Pulse Generator (CPG) (7) Frequency Control Register (FRQCR) The frequency control register (FRQCR) has control bits assigned for the following functions: clock output/non-output from the CKIO pin during software standby mode, the frequency multiplication ratio of PLL ...
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SH7201 Group 4.3 Clock Operating Modes Table 4.2 shows the relationship between the combinations of the mode control pins (MD_CLK1 and MD_CLK0) and the clock operating modes. Table 4.2 shows the usable frequency ranges in the clock operating modes. Table ...
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Section 4 Clock Pulse Generator (CPG) Table 4.3 Relationship between Clock Operating Mode and Frequency Range PLL Frequency Multiplier Clock Operating FRQCR PLL PLL Mode Setting Circuit 1 Circuit 2 0 H'1000 ON (×1) ON (×4) H'1001 ON (×1) ON ...
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SH7201 Group PLL Frequency Multiplier Clock Operating FRQCR PLL PLL Mode Setting Circuit 1 Circuit 2 0 H'1313 ON (×4) ON (×4) H'1315 ON (×4) ON (×4) H'1316 ON (×4) ON (×4) H'1333 ON (×4) ON (×4) H'1335 ON (×4) ...
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Section 4 Clock Pulse Generator (CPG) PLL Frequency Multiplier Clock FRQCR PLL PLL Operating Mode Setting Circuit 1 Circuit 2 2 H'1226 ON (×3) ON (×2) H'1303 ON (×4) ON (×2) H'1305 ON (×4) ON (×2) H'1306 ON (×4) ON ...
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SH7201 Group PLL Frequency Multiplier Clock FRQCR PLL PLL Operating Mode Setting Circuit 1 Circuit 2 3 H'1101 ON (×2) OFF H'1103 ON (×2) OFF H'1104 ON (×2) OFF H'1105 ON (×2) OFF H'1106 ON (×2) OFF H'1111 ON (×2) ...
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Section 4 Clock Pulse Generator (CPG) PLL Frequency Multiplier Clock FRQCR PLL PLL Operating Mode Setting Circuit 1 Circuit 2 3 H'1404 ON (×6) OFF H'1406 ON (×6) OFF H'1414 ON (×6) OFF H'1416 ON (×6) OFF H'1424 ON (×6) ...
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SH7201 Group 4.4 Register Descriptions The clock pulse generator has the following registers. Table 4.4 Register Configuration Register Name Frequency control register CKIO control register 4.4.1 Frequency Control Register (FRQCR) FRQCR is a 16-bit readable/writable register used to specify whether ...
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Section 4 Clock Pulse Generator (CPG) Initial Value Bit Bit Name 12 CKOEN 1 ⎯ STC[2:0] 000 ⎯ Page 84 of 1190 R/W Description R/W Clock Output Enable Specifies whether a clock is ...
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SH7201 Group Initial Value Bit Bit Name IFC[2:0] 000 3 RNGS PFC[2:0] 011 R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 R/W Description R/W CPU Clock Frequency Division Ratio These bits specify the frequency division ...
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Section 4 Clock Pulse Generator (CPG) 4.4.2 CKIO Control Register (CKIOCR) CKIOCR is an 8-bit readable/writable register used to control output of the CKIO pin. When this LSI is started in clock operating mode 3, writing 1 to this register ...
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SH7201 Group 4.5 Changing the Frequency The frequency of the internal clock (Iφ) and peripheral clock (Pφ) can be changed either by changing the multiplication rate of PLL circuit changing the division rates of divider. All of ...
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Section 4 Clock Pulse Generator (CPG) 4.5.2 Changing the Division Ratio Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is not the initial state, IFC[2:0] = B'000 and PFC[2:0] = ...
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SH7201 Group 4.6 Notes on Board Design 4.6.1 Note on Inputting External Clock Figure 4 example of connecting the external clock input. When putting the XTAL pin in open state, make sure the parasitic capacitance is less than ...
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Section 4 Clock Pulse Generator (CPG) 4.6.3 Note on Resonator Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in ...
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SH7201 Group Section 5 Exception Handling 5.1 Overview 5.1.1 Types of Exception Handling and Priority Exception handling is started by sources, such as resets, address errors, bus errors, register bank errors, interrupts, and instructions. Table 5.1 shows their priorities. When ...
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Section 5 Exception Handling Type Exception Handling Interrupts On-chip peripheral modules Instructions Trap instruction (TRAPA instruction) General illegal instructions (undefined code) Slot illegal instructions (undefined code placed directly after a delayed branch instruction * instructions * 3 , RESBANK instruction, ...
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SH7201 Group 5.1.2 Exception Handling Operations The exception handling sources are detected and begin processing according to the timing shown in table 5.2. Table 5.2 Timing of Exception Source Detection and Start of Exception Handling Exception Source Reset Power-on reset ...
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Section 5 Exception Handling When exception handling starts, the CPU operates as follows: Exception Handling Triggered by Reset (1) The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception handling vector table (PC ...
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SH7201 Group 5.1.3 Exception Handling Vector Table Before exception handling begins running, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception service routines. (The reset exception handling table ...
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Section 5 Exception Handling Exception Sources (Reserved by system) Trap instruction (user vector) External interrupts (IRQ, PINT), on-chip peripheral module interrupts * Note: * The vector numbers and vector table address offsets for each external interrupt and on- chip peripheral ...
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SH7201 Group 5.2 Resets 5.2.1 Input/Output Pins Table 5.5 shows the configuration of pins relating to the resets. Table 5.5 Pin Configuration Pin Name Symbol RES Power-on reset MRES Manual reset 5.2.2 Types of Reset A reset is the highest-priority ...
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Section 5 Exception Handling Conditions for Transition to Reset State RES H-UDI Command MRES Type High Manual Command other reset than H-UDI reset assert is set High Command other than H-UDI reset assert is set Notes: 1. Some registers are ...
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SH7201 Group (2) Power-On Reset by Means of H-UDI Reset Assert Command When the H-UDI reset assert command is set, this LSI enters the power-on reset state. Power-on reset by means of an H-UDI reset assert command is equivalent to ...
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Section 5 Exception Handling 5.2.4 Manual Reset Manual Reset by Means of MRES Pin (1) When the MRES pin is driven low, this LSI enters the manual reset state. To reset this LSI without fail, the MRES pin should be ...
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SH7201 Group 5.3 Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data read or written, as shown in table 5.7. Table 5.7 Bus Cycles and Address Errors Bus Cycle Bus Type Master Instruction CPU ...
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Section 5 Exception Handling 5.3.2 Address Error Exception Handling When an address error occurs, address error exception handling starts after the bus cycle in which the address error occurred ends* and execution of the instruction being executed completes. The CPU ...
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SH7201 Group 5.4 Bus Error 5.4.1 Bus Error Generation Source In bus monitor, notification of bus error occurrence to the CPU can be set. The notification is generated when incorrect address access or bus timeout is detected. For details, see ...
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Section 5 Exception Handling 5.5 Register Bank Errors 5.5.1 Register Bank Error Sources Bank Overflow (1) In the state where saving has already been performed to all register bank areas, bank overflow occurs when acceptance of register bank overflow exception ...
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SH7201 Group 5.6 Interrupts 5.6.1 Interrupt Sources Table 5.8 shows the sources that start up interrupt exception handling. These are divided into NMI, user breaks, H-UDI, IRQ, PINT, and on-chip peripheral modules. Table 5.8 Interrupt Sources Type NMI User break ...
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Section 5 Exception Handling 5.6.2 Interrupt Priority Level The interrupt priority order is predetermined. When multiple interrupts occur simultaneously (overlap), the interrupt controller (INTC) determines their relative priorities and starts processing according to the results. The priority order of interrupts ...
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SH7201 Group 5.6.3 Interrupt Exception Handling When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority ...
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Section 5 Exception Handling 5.7 Exceptions Triggered by Instructions 5.7.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal instructions, integer division exceptions, and FPU exceptions, as shown in table ...
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SH7201 Group 5.7.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception handling starts. The CPU operates as follows: 1. The exception service routine start address which corresponds to the vector number specified in the TRAPA instruction is ...
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Section 5 Exception Handling 5.7.5 Integer Division Exceptions When an integer division instruction performs division by zero or the result of integer division overflows, integer division instruction exception handling starts. The instructions that may become the source of division-by-zero exception ...
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SH7201 Group 4. After jumping to the address fetched from the exception handling vector table, program execution starts. The jump that occurs is not a delayed branch. The FPU exception flag field (Flag) of FPSCR is always updated regardless of ...
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Section 5 Exception Handling 5.9 Stack Status after Exception Handling Ends The status of the stack after exception handling ends is as shown in table 5.12. Table 5.12 Stack Status After Exception Handling Ends Exception Type Address error Interrupt Bus ...
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SH7201 Group Exception Type Register bank error (underflow) Trap instruction Slot illegal instruction General illegal instruction Integer division exception R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 Stack Status Start address of relevant SP RESBANK instruction SR Address of instruction SP after ...
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Section 5 Exception Handling 5.10 Usage Notes 5.10.1 Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four not, an address error will occur when the stack is accessed ...
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SH7201 Group Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC registers set the order of priority of each interrupt, allowing the user to process ...
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Section 6 Interrupt Controller (INTC) NMI IRQ7 to IRQ0 PINT7 to PINT0 (Interrupt request) UBC (Interrupt request) H-UDI (Interrupt request) ADC (Interrupt request) MTU2 (Interrupt request) RTC (Interrupt request) WDT (Interrupt request) IIC3 DMAC (Interrupt request) SCIF (Interrupt request) RCAN-ET ...
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SH7201 Group 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the INTC. Table 6.1 Pin Configuration Pin Name Nonmaskable interrupt input pin Interrupt request input pins 6.3 Register Descriptions The INTC has the following registers. These registers are ...
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Section 6 Interrupt Controller (INTC) Register Name Interrupt priority register 08 Interrupt priority register 09 Interrupt priority register 10 Interrupt priority register 11 Interrupt priority register 12 Interrupt priority register 13 Interrupt priority register 14 Interrupt priority register 15 Interrupt ...
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SH7201 Group 6.3.1 Interrupt Priority Registers 01, 02 (IPR01, IPR02, IPR05 to IPR16) IPR01, IPR02, and IPR05 to IPR16 are 16-bit readable/writable registers in which priority levels from are set for IRQ interrupts, PINT ...
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Section 6 Interrupt Controller (INTC) Register Name Bits Interrupt priority SCIF6 register 13 Interrupt priority DMAC5 register 14 Interrupt priority Reserved register 15 Interrupt priority SSI0 register 16 As shown in table 6.3, by setting the 4-bit ...
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SH7201 Group 6.3.2 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode for the external interrupt input pin NMI, and indicates the input level at the NMI pin. ICR0 is initialized by ...
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Section 6 Interrupt Controller (INTC) 6.3.3 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ7 to IRQ0 individually: low level, falling edge, rising edge, or both edges. ICR1 ...
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SH7201 Group 6.3.4 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7 to PINT0 individually: low level or high level. ICR2 is initialized by a power-on reset or ...
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Section 6 Interrupt Controller (INTC) Bit — — — — Initial value R/ Note: * Only 0 can be written to clear the flag after 1 is read. ...
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SH7201 Group 6.3.6 PINT Interrupt Enable Register (PINTER) PINTER is a 16-bit register that enables interrupt request inputs to external interrupt input pins PINT7 to PINT0. PINTER is initialized by a power-on reset or in deep standby mode. Bit: 15 ...
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Section 6 Interrupt Controller (INTC) 6.3.7 PINT Interrupt Request Register (PIRR) PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to PINT0. PIRR is initialized by a power-on reset or in deep standby mode. Bit: ...
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SH7201 Group 6.3.8 Bank Control Register (IBCR) IBCR is a 16-bit register that enables or disables use of register banks for each interrupt priority level. IBCR is initialized to H'0000 by a power-on reset or in deep standby mode. Bit: ...
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Section 6 Interrupt Controller (INTC) 6.3.9 Bank Number Register (IBNR) IBNR is a 16-bit register that enables or disables use of register banks and register bank overflow exception. IBNR also indicates the bank number to which saving is performed next ...
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SH7201 Group Initial Bit Bit Name Value BN[3:0]* 0000 Note: * Bits BN[3:0] are initialized at a manual reset. 6.3.10 DMA Transfer Request Enable Register 0 (DREQER0) DMA transfer request enable register 0 (DREQER0 8-bit ...
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Section 6 Interrupt Controller (INTC) 6.3.11 DMA Transfer Request Enable Register 1 (DREQER1) DMA transfer request enable register 1 (DREQER1 8-bit readable/writable register that enables/disables the SCIF (channels DMA transfer requests, and enables/disables CPU interrupt ...
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SH7201 Group 6.3.12 DMA Transfer Request Enable Register 2 (DREQER2) DMA transfer request enable register 2 (DREQER2 8-bit readable/writable register that enables/disables the SCIF (channels DMA transfer requests, and enables/disables CPU interrupt requests. DMA transfer ...
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Section 6 Interrupt Controller (INTC) 6.3.13 DMA Transfer Request Enable Register 3 (DREQER3) DMA transfer request enable register 3 (DREQER3 8-bit readable/writable register that enables/disables the ADC, MTU2 (channels 0 to 4), and RCAN-ET (channels 0 and 1) ...
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SH7201 Group 6.4 Interrupt Sources There are six types of interrupt sources: NMI, user break, H-UDI, IRQ, PINT, and on-chip peripheral modules. Each interrupt has a priority level (0 to 16), with 0 the lowest and 16 the highest. When ...
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Section 6 Interrupt Controller (INTC) 6.4.4 IRQ Interrupts IRQ interrupts are input from pins IRQ7 to IRQ0. As regard to the setting method of pins IRQ7 to IRQ0, see section 23, Pin Function Controller (PFC). For the IRQ interrupts, low-level, ...
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SH7201 Group 6.4.5 PINT Interrupts PINT interrupts are input from pins PINT7 to PINT0. As regard to the setting method of pins PINT7 to PINT0, see section 23, Pin Function Controller (PFC). Input of the interrupt requests is enabled by ...
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Section 6 Interrupt Controller (INTC) As every source is assigned a different interrupt vector, the source does not need to be identified in the exception service routine. A priority level in a range from can be set ...
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SH7201 Group Table 6.4 Interrupt Exception Handling Vectors and Priorities Interrupt Source Vector NMI 11 User break 12 H-UDI 14 IRQ IRQ0 64 IRQ1 65 IRQ2 66 IRQ3 67 IRQ4 68 IRQ5 69 IRQ6 70 IRQ7 71 R01UH0026EJ0300 Rev. 3.00 ...
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Section 6 Interrupt Controller (INTC) Interrupt Source Vector PINT PINT0 80 PINT1 81 PINT2 82 PINT3 83 PINT4 84 PINT5 85 PINT6 86 PINT7 87 ADC ADI 92 Page 138 of 1190 Interrupt Vector Interrupt Priority Vector Table (Initial Address ...
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SH7201 Group Interrupt Source Vector MTU2 MTU0 TGI0A 108 TGI0B 109 TGI0C 110 TGI0D 111 TCI0V 112 TCI0E 113 TCI0F 114 MTU1 TGI1A 116 TGI1B 117 TCI1V 120 TCI1U 121 MTU2 TGI2A 124 TGI2B 125 TCI2V 128 TCI2U 129 R01UH0026EJ0300 ...
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Section 6 Interrupt Controller (INTC) Interrupt Source Vector MTU2 MTU3 TGI3A 132 TGI3B 133 TGI3C 134 TGI3D 135 TCI3V 136 MTU4 TGI4A 140 TGI4B 141 TGI4C 142 TGI4D 143 TCI4V 144 MTU5 TGI5U 148 TGI5V 149 TGI5W 150 RTC ARM ...
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SH7201 Group Interrupt Source Vector WDT ITI 156 IIC3 IIC0 STPI0 157 NAKI0 158 RXI0 159 TXI0 160 TEI0 161 IIC1 STPI1 164 NAKI1 165 RXI1 166 TXI1 167 TEI1 168 IIC2 STPI2 170 NAKI2 171 RXI2 172 TXI2 173 ...
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Section 6 Interrupt Controller (INTC) Interrupt Source Vector DMAC DMAC0 DMINT0 176 DMAC1 DMINT1 177 DMAC2 DMINT2 178 DMAC3 DMINT3 179 SCIF SCIF0 BRI0 180 ERI0 181 RXI0 182 TXI0 183 SCIF1 BRI1 184 ERI1 185 RXI1 186 TXI1 187 ...
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SH7201 Group Interrupt Source Vector SCIF SCIF3 BRI3 192 ERI3 193 RXI3 194 TXI3 195 SCIF4 BRI4 196 ERI4 197 RXI4 198 TXI4 199 SCIF5 BRI5 200 ERI5 201 RXI5 202 TXI5 203 SCIF6 BRI6 204 ERI6 205 RXI6 206 ...
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Section 6 Interrupt Controller (INTC) Interrupt Source Vector SCIF SCIF7 BRI7 208 ERI7 209 RXI7 210 TXI7 211 DMAC DMINTA 212 DMAC4 DMINT4 216 DMAC5 DMINT5 217 DMAC6 DMINT6 218 DMAC7 DMINT7 219 RCAN- RCAN- ERS 228 ET ET0 OVR ...
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SH7201 Group Interrupt Source Vector RCAN- RCAN- ERS 234 ET ET1 OVR 235 SLE 236 RM0 237 RM1 238 SSI SSI0 244 SSI1 245 TMR TMR0 CMIA0 246 CMIB0 247 OVI0 248 TMR1 CMIA1 252 CMIB1 253 OVI1 254 R01UH0026EJ0300 ...
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Section 6 Interrupt Controller (INTC) 6.6 Operation 6.6.1 Interrupt Operation Sequence The sequence of interrupt operations is described below. Figure 6.2 shows the operation flow. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The ...
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SH7201 Group Program execution state No Interrupt? Yes No NMI? Yes User break? Yes Read exception handling vector table Save SR to stack Copy accept-interrupt level Save PC to stack Branch to interrupt exception service routine ...
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Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Handling Figure 6.3 shows the stack after interrupt exception handling. Address 4n – – Notes: 1. PC: Start address of the next instruction (return ...
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SH7201 Group 6.7 Interrupt Response Time Table 6.5 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction in the interrupt exception ...
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Section 6 Interrupt Controller (INTC) Item NMI Interrupt No Min. 5 Icyc + response register 2 Bcyc + time banking 1 Pcyc + Max. 6 Icyc + 2 Bcyc + 1 Pcyc + 2 (m1 + m2) ...
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SH7201 Group 2 Icyc + 3 Bcyc + 1 Pcyc IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) F: Instruction ...
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Section 6 Interrupt Controller (INTC) IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 6.6 Example of Pipeline Operation when ...
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SH7201 Group 2 Icyc + 3 Bcyc + 1 Pcyc IRQ Instruction (instruction replacing interrupt exception handling) First instruction in interrupt service routine [Legend] m1: Vector address read m2: Saving of SR (stack) m3: Saving of PC (stack) Figure 6.8 ...
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Section 6 Interrupt Controller (INTC) 6.8 Register Banks This LSI has fifteen register banks used to perform register saving and restoration required in the interrupt processing at high speed. Figure 6.10 shows the register bank configuration. Registers General registers Control ...
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SH7201 Group 6.8.1 Register Banks and Bank Control Registers Banked Register (1) The contents of the general registers (R0 to R14), global base register (GBR), multiply and accumulate registers (MACH and MACL), and procedure register (PR), and the vector table ...
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Section 6 Interrupt Controller (INTC) Figure 6.12 shows the timing for saving to a register bank. Saving to a register bank takes place between the start of interrupt exception handling and the start of fetching the first instruction in the ...
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SH7201 Group 6.8.3 Save and Restore Operations after Saving to All Banks If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the CPU in a state where saving has been performed to ...
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Section 6 Interrupt Controller (INTC) 6.8.4 Register Bank Exception There are two register bank exceptions (register bank errors): register bank overflow and register bank underflow. (1) Register Bank Overflow This exception occurs if, after data has been saved to all ...
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SH7201 Group 6.9 Data Transfer with Interrupt Request Signals Interrupt request signals can be used to activate the DMAC and transfer data. Interrupt sources that are specified to activate the DMAC are masked by setting the DMA transfer enable bit ...
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Section 6 Interrupt Controller (INTC) 6.10 Usage Note 6.10.1 Timing to Clear an Interrupt Source The interrupt source flags should be cleared in the interrupt handler. After clearing the interrupt source flag, "time from occurrence of interrupt request until interrupt ...
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SH7201 Group Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit ...
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Section 7 User Break Controller (UBC) Figure 7.1 shows a block diagram of the UBC. Internal bus CPU bus (I bus) (C bus) Access control IDB IAB MDB MAB FAB [Legend] BBR: Break bus cycle register BAR: Break address register ...
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SH7201 Group 7.2 Input/Output Pin Table 7.1 shows the pin configuration of the UBC. Table 7.1 Pin Configuration Pin Name Symbol UBCTRG UBC trigger 7.3 Register Descriptions The UBC has the following registers. Table 7.2 Register Configuration Channel Register Name ...
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Section 7 User Break Controller (UBC) 7.3.1 Break Address Register (BAR) BAR is a 32-bit readable/writable register. BAR specifies the address used as a break condition in each channel. The control bits CD[1:0] in the break bus cycle register (BBR) ...
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SH7201 Group 7.3.2 Break Address Mask Register (BAMR) BAMR is a 32-bit readable/writable register. BAMR specifies bits masked in the break address bits specified by BAR. BAMR is initialized to H'00000000 by a power-on reset or in deep standby, but ...
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Section 7 User Break Controller (UBC) 7.3.3 Break Data Register (BDR) BDR is a 32-bit readable/writable register. The control bits CD[1:0] in the break bus cycle register (BBR) select one of the two data buses for a break condition. BDR ...
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SH7201 Group 7.3.4 Break Data Mask Register (BDMR) BDMR is a 32-bit readable/writable register. BDMR specifies bits masked in the break data bits specified by BDR. BDMR is initialized to H'00000000 by a power-on reset or in deep standby, but ...
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Section 7 User Break Controller (UBC) 7.3.5 Break Bus Cycle Register (BBR) BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break interrupts, (2) including or excluding of the data bus value, (3) bus master ...
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SH7201 Group Initial Value Bit Bit Name 7, 6 CD[1: ID[1: RW[1: SZ[1:0] 00 [Legend] x: Don't care R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 R/W Description R/W C Bus Cycle/I Bus ...
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Section 7 User Break Controller (UBC) 7.3.6 Break Control Register (BRCR) BRCR sets the following conditions: 1. Specifies whether a start of user break interrupt exception processing by instruction fetch cycle is set before or after instruction execution. 2. Specifies ...
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SH7201 Group Initial Bit Bit Name Value 15 SCMFC0 0 14 SCMFC1 0 13 SCMFD0 0 12 SCMFD1 0 ⎯ All 0 R01UH0026EJ0300 Rev. 3.00 Sep 24, 2010 R/W Description R/W C Bus Cycle Condition Match Flag ...
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Section 7 User Break Controller (UBC) Initial Bit Bit Name Value 6 PCB1 0 5 PCB0 0 ⎯ All 0 Page 172 of 1190 R/W Description R/W PC Break Select 1 Selects the break timing of the ...