R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1199

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
16.5 SCIF Interrupts
17.3.1 I
(ICCR1)
17.3.2 I
(ICCR2)
17.3.3 I
(ICMR)
17.3.4 I
Register (ICIER)
Item
2
2
2
2
C Bus Control Register 1
C Bus Control Register 2
C Bus Mode Register
C Bus Interrupt Enable
Page
725
733
737
739
740
741
Revision (See Manual for Details)
Description amended
When the RIE bit is set to 0 and the REIE bit is set to
1, the SCIF requests only an ERI or a BRI interrupt
without requesting an RXI interrupt.
Table amended
Table amended
Table amended
Table amended
Table amended
Bit
7
Bit
1
Bit
2 to 0
Bit
5
Bit
4
Bit Name
ICE
Bit Name
IICRST
Bit Name
BC[2:0]
Bit Name
RIE
Bit Name
NAKIE
Initial
Value
0
Value
0
Initial
Value
000
Initial
Value
0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Bit Counter
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits
is indicated. With the I
transferred with one addition acknowledge bit. Should
be made between transfer frames. If these bits are set
to a value other than B'000, the setting should be made
while the SCL pin is low. The bit value returns to B'000
automatically at the end of a data transfer including the
acknowledge bit. And the value becomes B'111
automatically after the stop condition detection. These
bits are cleared by a power-on reset, in deep standby
mode, software standby mode, or module standby
mode. These bits are also cleared by setting the
IICRST bit of ICCR2 to 1. With the clocked synchronous
serial format, these bits should not be modified.
Description
IIC Control Part Reset
Resets bits BC[2:0] in ICMR and internal circuits. If this
bit is set to 1 when hang-up occurs because of
communication failure during I
BC[2:0] in ICMR and internal circuits can be reset.
Description
Receive Interrupt Enable
Enables or disables the receive data full interrupt
request (RXI)
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
RXI can be canceled by clearing the RDRF or RIE bit to
0.
0: Receive data full interrupt request (RXI) are disabled.
1: Receive data full interrupt request (RXI) are enabled.
Description
NACK Receive Interrupt Enable
Enables or disables the NACK detection, arbitration lost
and overrun error interrupt request (NAKI) when the
NACKF or AL/OVE bit in ICSR is set. NAKI can be
canceled by clearing the NACKF, AL/OVE, or NAKIE bit
to 0.
0: NACK receive interrupt request (NAKI) is disabled.
1: NACK receive interrupt request (NAKI) is enabled.
Description
I
0: SCL and SDA output is disabled. (Input to SCL and
1: This bit is enabled for transfer operations.
2
C Bus Interface 3 Enable
SDA is enabled.)
Main Revisions for This Edition
when receive data is transferred from
2
C bus format, the data is
2
Page 1171 of 1190
C bus operation, bits