R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 383

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
clock) after the end of the single operand transfer. This provides a margin in which continued
requests for DMA transfer on the same channel are rejected.
Figure 11.8 shows the period over which DMA request bit is masked when a level sense has been
selected.
Therefore, for a channel on which level sense has been selected, even when the DMA request
signal level is maintained (requesting further DMA transfer) well after the DMA request has been
accepted and handled, DMA requests on other channels, if they exist, are accepted. This is because
the DMA request on the channel on which level sense has been selected is not considered to exist
during the DMA request bit masking period.
In the case of sequential operand transfer, masking is only applied from the end of operand
transfer, i.e. when the byte count is 0. The DMA request is not masked while the byte count is
non-zero, so channel arbitration is executed without masking of the DMA request during the
actual unit transfer operation.
In the case of non-stop transfer, masking is only enabled from the end of the transfer operation, i.e.
when the byte count is 0.
If the DMA transfer is not done sequentially, the DMA request must be canceled within three
cycles after the end of single operand transfer.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
System clock
DMA state
DMA request input
(low level sense)
DMA acknowledge
output
DMA request bit
[Legend]
: Sampling point for DMA requests
Figure 11.8 Period over which DMA Request Bit is Masked
when a Level Sense is Selected
(Period of masking for the DMA request bit)
The period of the unit transfer operation in this example is short;
non-recognition of the DMA request during the masking period prevents a DMA
request that is cleared too late from affecting the next channel-arbitration period.
Read
Single operand transfer
Section 11 Direct Memory Access Controller (DMAC)
Write
Start of channel arbitration
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