R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 189

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Instruction fetch or data read/write of CPU, data
size, data contents, address value, and stop timing in the case of instruction fetch are break
conditions that can be set in the UBC. Since this LSI uses a Harvard architecture, instruction fetch
on the CPU bus (C bus) is performed by issuing bus cycles on the instruction fetch bus (F bus),
and data access on the C bus is performed by issuing bus cycles on the memory access bus (M
bus). The UBC monitors the C bus and internal bus (I bus).
7.1
1. The following break comparison conditions can be set.
• Address
• Data
• Bus cycle
• Read/write
• Operand size
2. In an instruction fetch cycle, it can be selected whether the start of user break interrupt
3. When a break condition is satisfied, a trigger signal is output from the UBCTRG pin.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Number of break channels: two channels (channels 0 and 1)
User break can be requested as the independent condition on channels 0 and 1.
Comparison of the 32-bit address is maskable in 1-bit units.
One of the three address buses (F address bus (FAB), M address bus (MAB), and I address bus
(IAB)) can be selected.
Comparison of the 32-bit data is maskable in 1-bit units.
One of the two data buses (M data bus (MDB) and I data bus (IDB)) can be selected.
Instruction fetch (only when C bus is selected) or data access
Byte, word, and longword
exception processing is set before or after an instruction is executed.
Features
Section 7 User Break Controller (UBC)
Section 7 User Break Controller (UBC)
Page 161 of 1190