R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1058

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 27 Advanced User Debugger II (AUD-II)
27.3.2
Operation starts in RAM monitor mode when AUDRST is asserted, AUDMD is driven high, and
then AUDRST is negated.
Figure 27.2 shows an example of a read operation, and figure 27.3 shows an example of a write
operation.
When AUDSYNC is asserted, input from the AUDATA pins begins. When a command, address,
or data (writing only) is input in the format shown in figure 27.1, execution of read/write access to
the specified address is started. During internal execution, the AUD returns Not Ready (B'0000).
When execution is completed, the Ready flag (B'0001) is returned (figures 27. 2 and 27. 3). Table
27.3 shows the Ready flag format.
In a read, data of the specified size is output when AUDSYNC is negated following detection of
this flag (figure 27. 2).
If a command other than the above is input in DIR, the AUD-II treats this as a command error,
disables processing, and sets bit 1 in the Ready flag to 1. If a read/write operation initiated by the
command specified in DIR causes a bus error, the AUD-II disables processing and sets bit 2 in the
Ready flag to 1 (figure 27. 4).
Bus error conditions are shown below.
1. Word access to address 4n+1 or 4n+3
2. Longword access to address 4n+1, 4n+2, or 4n+3
Table 27.3 Ready Flag Format
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Bit 3
Fixed at 0
Operation
Bit 2
0: Normal status
1: Bus error
Bit 1
0: Normal status
1: Command error
Bit 0
0: Not ready
1: Ready
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010