R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 335

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
11.3.2
DMCDADR is a register used to specify the start address of the transfer destination.
The value in this register is transferred to the working destination-address register at the start of
DMA transfer.
The default behavior is for the contents of the working destination-address register to be returned
on completion of each single operand transfer. However, the contents of the working destination-
address register are not returned in two cases: when the rotate setting (SAMOD = 011) is made for
the destination address and when the destination-address reload function is enabled. In the latter
case, the contents of the DMA reload destination address register (DMRDADRn) are returned to
this register on completion of DMA transfer.
This register must be set before transfer is initiated, regardless of whether the reload function is
enabled or disabled.
Notes: 1. Set this register so that DMA transfer is performed within the correctly aligned address
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
2. Only write to this register when single operand transfer is not in process on the
DMA Current Destination Address Register (DMCDADR)
Bit Name
CDA
R/W
R/W
boundaries for the transfer sizes listed below.
corresponding channel (the corresponding DASTS bit in the DMA arbitration status
register (DMASTS) is "0") and DMA transfer is disabled (DMST in the DMA activation
control register (DMSCNT) or DEN in DMA control register B for the channel
(DMCNTBn) is set to "0"). Operation is not guaranteed if this register is written to when
both conditions are not satisfied.
31
15
—
—
•
•
When the transfer size is set to 16 bits (SZSEL = "001"): (b0) = "0".
When the transfer size is set to 32 bits (SZSEL = "010"): (b1, b0) = (0, 0).
R/W
R/W
30
14
—
—
R/W
R/W
29
13
—
—
Initial
Value
Undefined R/W
R/W
R/W
28
12
—
—
R/W
R/W
27
11
—
—
R/W
R/W
R/W
26
10
—
—
Description
Holds destination address bits A31 to A0
R/W
R/W
25
—
—
9
R/W
R/W
24
—
—
8
CDA
CDA
R/W
R/W
23
—
—
7
Section 11 Direct Memory Access Controller (DMAC)
R/W
R/W
22
—
—
6
R/W
R/W
21
—
—
5
R/W
R/W
20
—
—
4
R/W
R/W
19
—
—
3
R/W
R/W
18
—
—
2
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R/W
R/W
17
—
—
1
R/W
R/W
16
—
—
0