R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 587

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
12.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag
When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits in TMDR_4
to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit in TMDR_4 is
set to 1.
In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA
and BFB bit settings of TMDR_3. For example, if the BFA bit in TMDR_3 is set to 1, TGRC_3
functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer
register for TGRA_4.
The TGFC bit and TGFD bit in TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are
operating as buffer registers.
Figure 12.121 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with
TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
TGRB_3, TGRA_4,
TGRB_4
TGRD_3, TGRC_4,
TGRD_4
TIOC3A
TIOC3B
TIOC3D
TIOC4A
TIOC4B
TIOC4D
TGFC
TIOC4C
TGFD
TGRC_3
H'0000
TGRA_3
Figure 12.121 Buffer Operation and Compare-Match Flags
Point b
in Reset Synchronous PWM Mode
Point a
Not set
TCNT3
Not set
Buffer transfer with
compare match A3
Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
TGRA_3,
TGRC_3
TGRB_3, TGRD_3,
TGRA_4, TGRC_4,
TGRB_4, TGRD_4
Page 559 of 1190