R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 805

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
18.3.1
SSICR is a readable/writable 32-bit register that controls the IRQ, selects the polarity status, and
sets operating mode.
SSICR is initialized to H'00000000 by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 29 —
28
27
26
25
24
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Control Register (SSICR)
SCKD SWSD SCKP SWSP SPDP SDTA PDTA DEL
DMEN
OIEN
IIEN
Bit Name
UIEN
DIEN
R/W
31
—
15
R
0
0
R/W
30
—
14
R
0
0
R/W
29
—
13
R
0
0
Initial
Value
All 0
0
0
0
0
0
DMEN UIEN OIEN IIEN DIEN
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R
R/W
R/W
R/W
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
Reserved
The read value is not guaranteed. The write value
should always be 0.
DMA Enable
Enables/disables the DMA request.
0: DMA request is disabled.
1: DMA request is enabled.
Underflow Interrupt Enable
0: Underflow interrupt is disabled.
1: Underflow Interrupt is enabled.
Overflow Interrupt Enable
0: Overflow interrupt is disabled.
1: Overflow interrupt is enabled.
Idle Mode Interrupt Enable
0: Idle mode interrupt is disabled.
1: Idle mode interrupt is enabled.
Data Interrupt Enable
0: Data interrupt is disabled.
1: Data interrupt is enabled.
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
CHNL[1:0]
23
—
R
0
7
0
R/W
R/W
22
0
6
0
CKDV[2:0]
R/W
R/W
21
0
5
0
Section 18 Serial Sound Interface (SSI)
DWL[2:0]
R/W
R/W
20
0
4
0
MUEN
R/W
R/W
19
0
3
0
R/W
18
—
R
0
2
0
Page 777 of 1190
SWL[2:0]
TRMD EN
R/W
R/W
17
0
0
1
R/W
R/W
16
0
0
0