R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 15

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 11 Direct Memory Access Controller (DMAC) ...................................299
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Features............................................................................................................................. 299
Input/Output Pins.............................................................................................................. 301
Register Descriptions ........................................................................................................ 302
11.3.1
11.3.2
11.3.3
11.3.4
11.3.5
11.3.6
11.3.7
11.3.8
11.3.9
11.3.10 DMA Activation Control Register (DMSCNT)................................................ 332
11.3.11 DMA Interrupt Control Register (DMICNT).................................................... 333
11.3.12 DMA Common Interrupt Control Register (DMICNTA) ................................. 334
11.3.13 DMA Interrupt Status Register (DMISTS) ....................................................... 335
11.3.14 DMA Transfer End Detection Register (DMEDET) ........................................ 336
11.3.15 DMA Arbitration Status Register (DMASTS).................................................. 338
Operation .......................................................................................................................... 340
11.4.1
11.4.2
11.4.3
Completion of DMA Transfer and Interrupts ................................................................... 347
11.5.1
11.5.2
11.5.3
Suspending, Restarting, and Stopping of DMA Transfer ................................................. 352
11.6.1
11.6.2
DMA Requests.................................................................................................................. 353
11.7.1
11.7.2
11.7.3
Determining DMA Channel Priority................................................................................. 357
11.8.1
11.8.2
11.8.3
Units of Transfer and Positioning of Bytes for Transfer................................................... 360
DMA Current Source Address Register (DMCSADR) .................................... 306
DMA Current Destination Address Register (DMCDADR) ............................ 307
DMA Current Byte Count Register (DMCBCT) .............................................. 308
DMA Reload Source Address Register (DMRSADR) ..................................... 309
DMA Reload Destination Address Register (DMRDADR) ............................. 310
DMA Reload Byte Count Register (DMRBCT) ............................................... 311
DMA Mode Register (DMMOD) ..................................................................... 312
DMA Control Register A (DMCNTA) ............................................................. 318
DMA Control Register B (DMCNTB) ............................................................. 326
DMA Transfer Mode ........................................................................................ 340
DMA Transfer Condition.................................................................................. 342
DMA Activation ............................................................................................... 346
Completion of DMA Transfer........................................................................... 347
DMA Interrupt Requests................................................................................... 348
DMA End Signal Output .................................................................................. 350
Suspending and Restarting DMA Transfer ....................................................... 352
Stopping DMA Transfer on Any Channel ........................................................ 352
Sources of DMA Requests................................................................................ 353
Synchronous Circuits for DMA Request Signals.............................................. 353
Sense Mode for DMA Requests........................................................................ 354
Channel Priority Order...................................................................................... 357
Operation during Multiple DMA Requests....................................................... 357
Output of the DMA Acknowledge and DNA Active Signals ........................... 358
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