R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 359

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
Note: When the software trigger is selected as the DMA request source, the DMA request bit
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
0
(DREQ) can be set to "1" regardless of the settings of the DMA transfer enable bit (DEN)
and DMAC module activation bit (DMST) and whether or not a transfer operation is
currently in progress. However, even if the software trigger is selected as the DMA request
source, only clear the DMA request bit (DREQ) to "0" or write to the DMAC internal state
clearing bit (DSCLR) when a transfer operation is not in process on the corresponding
channel (the corresponding DASTS bit in the DMA arbitration status register (DMASTS) is
"0") and DMA transfer has been disabled (DMST in the DMA activation control register
(DMSCNT) or DEN in the DMA control register B (DMCNTBn) is set to "0"). Operation is not
guaranteed if this register is written to when these conditions are not satisfied.
Bit Name
DSCLR
Initial
Value
0
R/W
R/W
Description
DMA Internal State Clear
Writing a "1" to this bit stops DMA transfer in the
middle of a sequence of DMA transfer, suspending the
remainder of the transfer and initializing the internal
state of the DMAC. Writing a "1" to this bit only clears
the transfer state of the DMAC internal circuit. The
other registers are not initialized. Writing "0" is invalid
and a "1" written to this bit is not retained. This bit is
always read as "0".
Note: This bit must only be written to when the
When reading:
Always read as "0"
When writing:
0: Invalid
1: Initializes the DMAC's internal state
corresponding channel is not in the midst of
single operand transfer (DASTS in the channel
corresponding to the DMA arbitration status
register (DMASTS) is "0") and DMA transfer has
been disabled (DMST in the DMA activation
control register (DMSCNT) or DEN in DMA
control register B (DMCNTBn) is set to "0").
Operation is not guaranteed when this bit is
written to while these conditions do not apply.
Section 11 Direct Memory Access Controller (DMAC)
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