R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 810

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 18 Serial Sound Interface (SSI)
Page 782 of 1190
Bit
6 to 4
Bit Name
CKDV[2:0]
Initial
Value
000
R/W
R/W
Description
Serial Oversample Clock Divide Ratio
Sets the ratio between oversample clock*
(AUDIO_CLK, or AUDIO_X1 and AUDIO_X2) and the
serial bit clock. In addition, combining these bits and the
CKDV3 bit in the standby control register enables to
divide the clock further by 1/4. This bit is ignored if
SCKD = 0. The serial bit clock is used in the shift
register and is provided on the SSISCK module pin.
•
000: Serial bit clock frequency = Oversample clock Frequency/1
001: Serial bit clock frequency = Oversample clock frequency/2
010: Serial bit clock frequency = Oversample clock frequency/4
011: Serial bit clock frequency = Oversample clock frequency/8
100: Serial bit clock frequency = Oversample clock frequency/16
101: Serial bit clock frequency = Oversample clock frequency/6
110: Serial bit clock frequency = Oversample clock frequency/12
111: Setting prohibited
•
000: Serial bit clock frequency = Oversample clock Frequency/4
001: Serial bit clock frequency = Oversample clock frequency/8
010: Serial bit clock frequency = Oversample clock frequency/16
011: Serial bit clock frequency = Oversample clock frequency/32
100: Serial bit clock frequency = Oversample clock frequency/64
101: Serial bit clock frequency = Oversample clock frequency/24
110: Serial bit clock frequency = Oversample clock frequency/48
111: Setting prohibited
Note: * AUDIO_X1 and AUDIO_X2 is selected as
When CKDV3 = 1
When CKDV3 = 0
oversample clock when the PD0MD0 bit in
the port D control register (PDCR1) of PFC is
set to 0, and AUDIO_CLK is selected when
the bit is set to 1.
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010