R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 157

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
Note:
6.3.10
DMA transfer request enable register 0 (DREQER0) is an 8-bit readable/writable register that
enables/disables the IIC3 DMA transfer requests, and enables/disables CPU interrupt requests.
DMA transfer request enable register 0 is initialized by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
3 to 0
Bit
7
6
5
4
3
2
1
0
* Bits BN[3:0] are initialized at a manual reset.
Bit Name
Reserved
Reserved
IIC3 2ch TX
IIC3 2ch RX
IIC3 1ch TX
IIC3 1ch RX
IIC3 0ch TX
IIC3 0ch RX
DMA Transfer Request Enable Register 0 (DREQER0)
Bit Name
BN[3:0]*
Initial value:
Initial
Value
0000
Initial
Value
0
0
0
0
0
0
0
0
R/W:
Bit:
R/W
Reserved
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
R/W
R
R/W
0
6
Description
Bank Number
These bits indicate the bank number to which saving is
performed next. When an interrupt using register banks
is accepted, saving is performed to the register bank
indicated by these bits, and BN is incremented by 1.
After BN is decremented by 1 due to execution of a
RESBANK (restore from register bank) instruction,
restoration from the register bank is performed.
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
2ch TX
IIC3
R/W
0
5
request enabled
disabled
2ch RX
IIC3
R/W
0
4
1ch TX
R/W
IIC3
0
3
1ch RX
R/W
IIC3
0
2
0ch TX
IIC3
R/W
1
0
Section 6 Interrupt Controller (INTC)
0ch RX
R/W
IIC3
0
0
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