R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 103

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
The clock pulse generator blocks function as follows:
(1)
PLL circuit 1 multiplies the input clock frequency from the CKIO pin by 1, 2, 3, 4, 6, or 8. The
multiplication rate is set by the frequency control register. When this is done, the phase of the
rising edge of the bus clock is controlled so that it will agree with the phase of the rising edge of
the CKIO pin.
(2)
PLL circuit 2 multiplies the input clock frequency from the crystal oscillator or EXTAL pin by 2
or 4. The multiplication rate is fixed according to the clock operating mode. The clock operating
mode is specified by the MD_CLK1 and MD_CLK0 pins. For details on the clock operating
mode, see table 4.2.
Note that the settings of these pins cannot be changed during operation. If changed, the operation
of this LSI cannot be guaranteed.
(3)
The crystal oscillator is an oscillation circuit in which a crystal resonator is connected to the
XTAL pin or EXTAL pin. This can be used according to the clock operating mode.
(4)
Divider generates a clock signal at the operating frequency used by the CPU or peripheral clock.
The operating frequency can be 1, 1/2, 1/3, 1/4, 1/6, 1/8, or 1/12 times the output frequency of
PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division
ratio is set in the frequency control register (FRQCR).
(5)
The clock frequency control circuit controls the clock frequency using the MD_CLK1 and
MD_CLK0 pins and the frequency control register (FRQCR).
(6)
The standby control circuit controls the states of the clock pulse generator and other modules
during clock switching, or in sleep, software, and deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
PLL Circuit 1
PLL Circuit 2
Crystal Oscillator
Divider
Clock Frequency Control Circuit
Standby Control Circuit
Section 4 Clock Pulse Generator (CPG)
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