R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 251

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
Auto-Refresh Request Interval and DRFC Set Value:
SDRAMC includes a 12-bit refresh counter that generates auto-refresh requests at fixed intervals.
The following equation is used to calculate the set value for the DRFC bits from the auto-refresh
request interval.
Auto-refresh requests are not accepted while SDRAM is being accessed; they must wait until the
access completes. However, the counter value is updated regardless or whether or not the request
was accepted. Note that if two or more auto-refresh requests are generated while SDRAM is being
accessed, the second and subsequent requests are ignored.
9.4.9
SDIR0 specifies the SDRAM initialization sequence timing.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
31 to 11 ⎯
10 to 8
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
DRFC = (Auto-refresh request interval / Bus clock cycle) – 1
SDRAM Initialization Register 0 (SDIR0)
Bit Name
DPC[2:0]
31
15
—
—
R
R
0
0
30
14
—
—
R
R
0
0
29
13
—
—
Initial
Value
All 0
Undefined R/W
R
R
0
0
28
12
—
—
R
R
0
0
27
11
—
—
R
R
0
0
R/W
R
R/W
26
10
—
—
R
0
DPC[2:0]
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Initialization Precharge Cycle Count Setting
These bits specify the number of precharge cycles in
the SDRAM initialization sequence.
000: 3 cycles
001: 4 cycles
111: 10 cycles
R/W
25
—
—
R
0
9
:
R/W
24
—
—
R
0
8
R/W
23
—
—
R
0
7
DARFC[3:0]
R/W
22
—
—
R
0
6
R/W
21
—
—
R
0
5
Section 9 Bus State Controller (BSC)
R/W
20
—
—
R
0
4
R/W
19
—
—
R
0
3
R/W
DARFI[3:0]
18
—
—
R
0
2
Page 223 of 1190
R/W
17
—
—
R
0
1
R/W
16
—
—
R
0
0