R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 135

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
Section 5 Exception Handling
5.6.3
Interrupt Exception Handling
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI
is always accepted, but other interrupts are only accepted if they have a priority level higher than
the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, interrupt exception handling begins. In interrupt exception
handling, the CPU fetches the exception service routine start address which corresponds to the
accepted interrupt from the exception handling vector table, and saves SR and the program counter
(PC) to the stack. In the case of interrupt exception handling other than the NMI or user break,
with usage of the register banks enabled, general registers R0 to R14, control register GBR,
system registers MACH, MACL, and PR, and the vector number of the interrupt exception
handling to be executed are saved in the register banks. In the case of exception handling due to an
address error, bus error, NMI interrupt, user break interrupt, or instruction, saving is not performed
to the register banks. If saving has been performed to all register banks (0 to 14), automatic saving
to the stack is performed instead of register bank saving. In this case, an interrupt controller setting
must have been made so that register bank overflow exceptions are not accepted (the BOVE bit in
IBNR of the INTC is 0). If the interrupt controller is set to accept register bank overflow
exceptions (the BOVE bit in IBNR of INTC is set to 1), a register bank overflow exception will
occur. Next, the priority level value of the accepted interrupt is written to the I3 to I0 bits in SR.
For NMI, however, the priority level is 16, but the value set in the I3 to I0 bits is H'F (level 15).
Then, after jumping to the start address of the interrupt exception service routine fetched from the
exception handling vector table, program execution starts. The jump that occurs is not a delayed
branch. See section 6.6, Operation, for further details of interrupt exception handling.
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Sep 24, 2010