R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1201

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R0K572011S000BE

Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr

Specifications of R0K572011S000BE

Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
18.2 Input/Output Pins
Table 18.1 Pin Assignments
18.3.1 Control Register (SSICR)
18.4.1 Bus Format
Table 18.3 Bus Format for SSI
Module
18.4.2 Non-Compressed Modes
(3) Master Receiver
(4) Master Transmitter
(5) Operating Setting Related to
Word Length
Item
Page
775
778
779
789
790
790
Revision (See Manual for Details)
Table amended
Table amended
Table amended
Table amended
Description amended
The non-compressed modes support all serial audio
streams split into channels. It supports I
format as well as many more variants on these
modes.
Description amended
... select signals are internally derived from the
oversampling clock.
Description amended
... signals are internally derived from the oversampling
clock.
Description amended
All bits related to the SSICR's word length are valid in
non-compressed modes. The SSI module supports
many configurations, but the formats described below
are I
first right-aligned.
Pin Name
AUDIO_CLK
AUDIO_X1
AUDIO_X1
Bit
14
Bit
15
TRMD
SCKD
2
S compatible, MSB-first left-aligned, and MSB-
Bit Name
SWSD
Bit Name
SCKD
Non-Compressed
Slave Receiver
0
0
Number of Pins
1
1
1
Initial
Value
0
Initial
Value
0
R/W
R/W
R/W
R/W
Non-Compressed
Slave Transmitter
1
0
I/O
Input
Input
Output
Description
Serial Bit Clock Direction
0: Serial bit clock is input, slave mode.
1: Serial bit clock is output, master mode.
Note: Only the following settings are allowed:
Description
Serial WS Direction
0: Serial word select is input, slave mode.
1: Serial word select is output, master mode.
Note: Only the following settings are allowed:
(SCKD, SWSD) = (0,0) and (1,1). Other settings
are prohibited.
(SCKD, SWSD) = (0,0) and (1,1). Other settings
are prohibited.
Description
Crystal oscillator for audio (Oversample clock)
External clock for audio (Oversample clock)
Main Revisions for This Edition
Non-Compressed
Master Receiver
0
1
2
Page 1173 of 1190
S compatible
Non-Compressed
Master Transmitter
1
1

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