R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 159

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
6.3.12
DMA transfer request enable register 2 (DREQER2) is an 8-bit readable/writable register that
enables/disables the SCIF (channels 4 to 7) DMA transfer requests, and enables/disables CPU
interrupt requests.
DMA transfer request enable register 2 is initialized by a power-on reset or in deep standby mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
7
6
5
4
3
2
1
0
Bit Name
SCIF 7ch TX
SCIF 7ch RX
SCIF 6ch TX
SCIF 6ch RX
SCIF 5ch TX
SCIF 5ch RX
SCIF 4ch TX
SCIF 4ch RX
DMA Transfer Request Enable Register 2 (DREQER2)
Initial value:
Initial
Value
0
0
0
0
0
0
0
0
R/W:
Bit:
7ch TX
SCIF
R/W
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
7ch RX
SCIF
R/W
0
6
Description
DMA Transfer Request Enable Bits
These bits enable/disable DMA transfer requests, and
enable/disable CPU interrupt requests.
0: DMA transfer request disabled, CPU interrupt
1: DMA transfer request enabled, CPU interrupt request
6ch TX
SCIF
R/W
0
5
request enabled
disabled
6ch RX
SCIF
R/W
0
4
5ch TX
SCIF
R/W
0
3
5ch RX
SCIF
R/W
0
2
4ch TX
SCIF
R/W
1
0
Section 6 Interrupt Controller (INTC)
4ch RX
SCIF
R/W
0
0
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