R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 777
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 777 of 1222
- Download datasheet (8Mb)
SH7201 Group
17.4.2
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to
figures 17.5 and 17.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the WAIT bit in ICMR and bits CKS[3:0] in ICCR1. (Initial
2. Read the BBSY flag in ICCR2 to confirm that the bus is released. Set the MST and TRS bits in
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
setting)
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP. (Start condition
issued) This generates the start condition.
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP. SCL is fixed low until the transmit data is prepared or
the stop condition is issued.
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR = 1) from the
receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
Master Transmit Operation
Section 17 I
2
C Bus Interface 3 (IIC3)
Page 749 of 1190
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