R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 753

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
16.5
The SCIF has four interrupt sources: transmit FIFO data empty (TXI), receive error (ERI), receive
FIFO data full (RXI), and break (BRI).
Table 16.12 shows the interrupt sources and their order of priority. The interrupt sources are
enabled or disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt
request is sent to the interrupt controller for each of these interrupt sources.
When a TXI request is enabled by the TIE bit and the TDFE flag in the serial status register
(SCFSR) is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data
transfer performed by this TXI interrupt request. At this time, an interrupt request is not sent to the
CPU.
When an RXI request is enabled by the RIE bit, and the RDF flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer
performed by this RXI interrupt request. At this time, an interrupt request is not sent to the CPU.
The RXI interrupt request caused by the DR flag is generated only in asynchronous mode.
When the RIE bit is set to 0 and the REIE bit is set to 1, the SCIF requests only an ERI or a BRI
interrupt without requesting an RXI interrupt.
The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that
there is receive data in SCFRDR.
Table 16.12 SCIF Interrupt Sources
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Interrupt
Source
BRI
ERI
RXI
TXI
SCIF Interrupts
Description
Interrupt initiated by break (BRK) or overrun error
(ORER)
Interrupt initiated by receive error (ER)
Interrupt initiated by receive FIFO data full (RDF) or
data ready (DR)
Interrupt initiated by transmit FIFO data empty
(TDFE)
Section 16 Serial Communication Interface with FIFO (SCIF)
DMAC
Activation
Not possible
Not possible
Possible
Possible
Priority on
Reset Release
High
Low
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