R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 51

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R0K572011S000BE

Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr

Specifications of R0K572011S000BE

Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
SH7201 Group
(2)
PR stores the return address of a subroutine call using a BSR, BSRF, or JSR instruction, and is
referenced by a subroutine return instruction (RTS).
(3)
PC points four bytes ahead of the instruction being executed.
2.1.4
For the nineteen 32-bit registers comprising general registers R0 to R14, control register GBR, and
system registers MACH, MACL, and PR, high-speed register saving and restoration can be carried
out using a register bank. The register contents are automatically saved in the bank after the CPU
accepts an interrupt that uses a register bank. Restoration from the bank is executed by issuing a
RESBANK instruction in an interrupt processing routine.
This LSI has 15 banks. For details, see the SH-2A, SH2A-FPU Software Manual and section 6.8,
Register Banks.
2.1.5
Table 2.1 lists the values of the registers after a reset.
Table 2.1
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Classification
General registers
Control registers
System registers
Procedure Register (PR)
Program Counter (PC)
Register Banks
Initial Values of Registers
Initial Values of Registers
Register
R0 to R14
R15 (SP)
SR
GBR, TBR
VBR
MACH, MACL, PR
PC
Initial Value
Undefined
address table
Bits I[3:0] are 1111 (H'F), BO and CS are
0, reserved bits are 0, and other bits are
undefined
Undefined
Value of the program counter in the vector
address table
Value of the stack pointer in the vector
Undefined
H'00000000
Page 23 of 1190
Section 2 CPU

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