R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 392

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R0K572011S000BE

Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr

Specifications of R0K572011S000BE

Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 11 Direct Memory Access Controller (DMAC)
11.12
Transfer speeds are calculated as shown below.
(1)
• DMA transfer mode: cycle-stealing transfer mode/pipelined transfer mode
• Transfer unit (one data size): properly aligned 32-bit data
• Operating clock: 60 MHz
• Number of cycles for access to external devices:
(2)
• Cycle-stealing transfer mode
• Pipelined transfer mode
Note: During transfer in the pipelined transfer mode, most read and write cycles overlap.
An example of the calculation of transfer speed is given below.
(a)
Maximum speed of transfer between on-chip RAM (0 wait) and on-chip RAM (0 wait).
• Cycle-stealing transfer mode
• Pipelined transfer mode
Page 364 of 1190
four cycles for reading; and
two cycles for writing.
Pipelined transfer through a single BIU is not possible. See section 11.4.1 (2), Pipelined
Transfer Mode.
Conditions for Calculation
Formulae Used in Calculation
Transfer between On-chip RAM
(data size in unit data transfer) / (number of read cycles + number of write cycles +
one idle cycle) × operating clock
(data size in unit data transfer) / (whichever is larger of number of read or write cycles) ×
operating clock
4 bytes / (1 read cycle + 1 write cycle + 1 idle cycle) × 60 MHz = 79.8 Mbytes/sec
Transfer Speed
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010

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