R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 1203

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
18.4.2 Non-Compressed Modes
(6) Multi-channel Formats
Figure 18.8 Multichannel Format
(6 Channels with High Padding)
Figure 18.9 Multichannel Format
(8 Channels; Transmitting and
Receiving in the order of Padding
Bits and Serial Data; with
Padding)
(7) Bit Setting Configuration
Format
Figure 18.13 Inverted Padding
Polarity
18.4.4 Transmit Operation
18.4.5 Receive Operation
18.4.7 Serial Bit Clock Control
18.5.1 Limitations from Overflow
during Receive DMA Operation
Item
Page
795
796
797
801
804
808
809
Revision (See Manual for Details)
Figure title amended
Figure title amended
Figure amended
As basic sample format configuration except SPDP = 1
SSISCK
SSIWS
SSIDATA TD28
Note amended
Note: * Input clock from the SSISCK pin when SCKD
Note amended
Note: * Input clock from the SSISCK pin when SCKD
Description amended
If the serial clock direction is set to output (SCKD = 1),
this module is in clock master mode, and the shift
register uses the oversampling clock or a divided
oversampling clock as the bit clock. The oversampling
clock is
oversampling clock division ratio bits (CKDV) in
SSICR for use as the bit clock by the shift register.
Description amended
... Therefore, data to be received at the L channel
may sometimes be received at the R channel if an
overflow occurs, for example, under the following
condition: the control register (SSICR) has a 32-bit
setting for both data word length (DWL2 to DWL0)
and system word length (SWL2 to SWL0).
Oversampling clock
= 0.
= 0.
Oversampling clock
1
divided by the ratio specified by the serial
1
TD31 TD30 TD29 TD28
1st Channel
1
Main Revisions for This Edition
when SCKD = 1.
when SCKD = 1.
1
TD31 TD30 TD29 TD28
2nd Channel
Page 1175 of 1190
1
1
TD31