SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 165

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Core Logic Module
Power Management SMI Status Reporting Registers
The Core Logic module updates status registers to reflect
the SMI sources. Power management SMI sources are the
device idle timers, address traps, and general purpose I/O
pins.
Power management events are reported to the GX1 mod-
ule through the active low SMI# signal. When an SMI is ini-
tiated, the SMI# signal is asserted low and is held low until
all SMI sources are cleared. At that time, SMI# is de-
asserted.
All SMI sources report to the Top Level SMI Status register
(F1BAR0+I/O Offset 02h) and the Top Level SMI Status
Mirror register (F1BAR0+I/O Offset 00h). The Top SMI Sta-
tus and Status Mirror registers are the top level of hierarchy
for the SMI Handler in determining the source of an SMI.
AMD Geode™ SC1200/SC1201 Processor Data Book
GX1
Module
Core Logic
Module
SMI# Asserted
Figure 6-11. General Purpose Timer and UDEF Trap SMI Tree Example
GTMR_TRP_SMI
top-level source
Read to Clear
to determine
F1BAR0+I/O
Top Level
Bits [15:10]
Offset 02h
Other_SMI
Other_SMI
Bits [8:0]
of SMI
Bit 9
(External SMI)
If Bit X = 1
If bit 9 = 1,
Source of SMI
is GP Timer or UDEF Trap
SMM software reads SMI Header
SMI de-asserted after all SMI Sources are Cleared
(i.e., Top and Second Levels - note some sources may have a Third Level)
These two registers are identical except that reading the
register at F1BAR0+I/O Offset 02h clears the status.
Since all SMI sources report to the Top Level SMI Status
register, many of its bits combine a large number of events
requiring a second level of SMI status reporting. The sec-
ond level of SMI status reporting is set up very much like
the top level. There are two status reporting registers, one
“read only” (mirror) and one “read to clear”. The data
returned by reading either offset is the same, the difference
between the two being that the SMI can not be cleared by
reading the mirror register.
Figure 6-11 shows an example SMI tree for checking and
clearing the source of General Purpose Timers and the
User Defined Trap generated SMI.
If Bit X = 0
(Internal SMI)
UDEF3_TRP_SMI
UDEF2_TRP_SMI
UDEF1_TRP_SMI
PCI_TRP_SMI
Second Level
Read to Clear
source of SMI
F1BAR0+I/O
to determine
second-level
GPT2_SMI
GPT1_SMI
Offset 06h
Bits [15:6]
RSVD
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Call internal SMI handler
to take appropriate action
32579B
Take
Appropriate
Action
165