SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 262

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

6.4.4
The register designated as Function 3 (F3) is used to con-
figure the PCI portion of support hardware for the audio
registers. The bit formats for the PCI Header registers are
given in Table 6-37.
262
Index 00h-01h
Index 02h-03h
Index 04h-05h
Index 06h-07h
Index 08h
Index 09h-0Bh
Index 0Ch
Index 0Dh
Index 0Eh
Index 0Fh
Index 10h-13h
This register sets the base address of the memory mapped audio interface control register block. This is a 128-byte block of registers
used to control the audio FIFO and codec interface, as well as to support VSA SMIs. Bits [11:0] are read only (0000 0000 0000), indicat-
ing a 4 KB memory address range. Refer to Table 6-38 on page 263 for the audio configuration register bit formats and reset values.
Index 14h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
Index 30h-FFh
31:12
15:3
11:0
Bit
2
1
0
Audio Registers - Function 3
Description
Reserved. (Read Only)
Bus Master. Allow the Core Logic module bus mastering capabilities.
0: Disable.
1: Enable. (Default)
This bit must be set to 1.
Memory Space. Allow the Core Logic module to respond to memory cycles from the PCI bus.
0: Disable.
1: Enable.
This bit must be enabled to access memory offsets through F3BAR0 (See F3 Index 10h).
Reserved. (Read Only)
Audio Interface Base Address.
Address Range. (Read Only)
32579B
Table 6-37. F3: PCI Header Registers for Audio Configuration
Base Address Register - F3BAR0 (R/W)
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Cache Line Size Register (RO)
Device Revision ID Register (RO)
PCI Latency Timer Register (RO)
PCI Class Code Register (RO)
PCI Command Register (R/W)
Subsystem Vendor ID (RO)
PCI Status Register (RO)
PCI BIST Register (RO)
PCI Header Type (RO)
Subsystem ID (RO)
Reserved
Reserved
A Base Address register (F3BAR0), located in the PCI
Header registers of F3, is used for pointing to the register
space designated for support of audio, described later in
this section.
AMD Geode™ SC1200/SC1201 Processor Data Book
Core Logic Module - Audio Registers - Function 3
Reset Value: 00000000h
Reset Value: 040100h
Reset Value: 100Bh
Reset Value: 100Bh
Reset Value: 0503h
Reset Value: 0000h
Reset Value: 0280h
Reset Value: 0503h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h