SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 406

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Note 1.
406
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2CYC
CYC
DS
DH
DVS
DVH
FS
LI
MLI
UI
AZ
ZAH
ZAD
ENV
SR
RFS
RP
IORDYZ
ZIORDY
ACK
SS
t
ing for the other agent to respond with a signal before proceeding. t
is a limited timeout with a defined minimum. t
UI
, t
Parameter
Typical sustained average two cycle time
Two cycle time allowing for clock variations
(from rising edge to next rising edge or from
falling edge to next falling edge of STROBE)
Cycle time allowing for asymmetry and clock
variations (from STROBE edge to STROBE
edge)
Data setup time (at recipient)
Data hold time (at recipient)
Data valid setup time at sender (from data
bus being valid until STROBE edge)
Data valid hold time at sender (from
STROBE edge until data may become
invalid)
First STROBE time (for device to first negate
IDE_IRDY[0:1] (DSTROBE[0:1]) from
IDE_IOW[0:1]# (STOP[0:1]) during a data in
burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output drivers to
release (from being asserted or negated)
Minimum delay time required for output driv-
ers to assert or negate (from released state)
Envelope time (from IDE_DACK[0:1]# to
IDE_IOW[0:1]# (STOP[0:1]) and
IDE_IOR[0:1]# (HDMARDY[0:1]#) during
data out burst initiation)
STROBE to DMARDY time (if DMARDY# is
negated before this long after STROBE
edge, the recipient receives no more than
one additional data WORD)
Ready-to-final-STROBE time (no STROBE
edges are sent this long after negation of
DMARDY#)
Ready-to-pause time (time that recipient
waits to initiate pause after negating
DMARDY#)
Pull-up time before allowing IDE_IORDY[0:1]
to be released
Minimum time device waits before driving
IDE_IORDY[0:1]
Setup and hold times for IDE_DACK[0:1]#
(before assertion or negation)
Time from STROBE edge to negation of
IDE_DREQ[0:1] or assertion of
IDE_IOW[0:1]# (STOP[0:1]) (when sender
terminates a burst)
MLI
, and t
LI
indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipient) is wait-
32579B
Table 9-30. IDE UltraDMA Data Burst Timing Parameters
LI
is a limited time-out with a defined maximum.
Min
240
235
114
160
15
70
20
20
20
20
50
5
6
0
0
0
0
0
Mode 0
Max
230
150
10
70
50
75
20
UI
is an unlimited interlock with no maximum time value. t
Min
160
156
125
75
10
48
20
20
20
20
50
5
0
0
6
0
0
0
AMD Geode™ SC1200/SC1201 Processor Data Book
Mode 1
Max
200
150
10
70
30
60
20
Min
120
117
100
55
34
20
20
20
20
50
7
5
6
0
0
0
0
0
Mode 2
Max
170
150
10
70
20
50
20
Electrical Specifications
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
Note 1
Note 1
Note 1
MLI