SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 86

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

4.5.4
The SuperI/O module requires a 48 MHz input for Fast
infrared (FIR), UART, and other functions. This clock is sup-
plied by PLL4 using a multiplier value of 576/(108x3) to
generate 48 MHz.
4.5.5
The Core Logic module requires the following clock
sources:
Real-Time Clock (RTC)
RTC requires a 32.768 KHz clock which is supplied directly
from an internal low-power crystal oscillator. This oscillator
uses battery power and has very low current consumption.
USB
The USB requires a 48 MHz input which is supplied by
PLL4. The required total frequency accuracy and slow jitter
for USB is 500 PPM; edge to edge jitter is ±1.2%.
ACPI
The ACPI logic block uses a 14.32 MHz clock supplied by
PLL6. PLL6 creates this clock from the 32.768 KHz clock,
with a multiplier value of 6992/4 to output a 57.278 MHz
clock that is divided by 4.
External PCI
The PCI Interface uses a 33.3 MHz clock that is created by
PLL5 and divided by 2. PLL5 uses the 27 MHz clock, to
output a 66.67 MHz clock. PLL5 has a frequency accuracy
of ± 0.1%.
86
SuperI/O Clocks
Core Logic Module Clocks
32579B
AC97
The SC1200/SC1201 processor generates the 24.576
MHz clock required by the audio codec. Therefore, no crys-
tal need be included for the audio codec on the system
board.
PLL3 uses the crystal oscillator clock, to generate a 24.576
MHz clock. This clock is driven on the AC97_CLK ball. The
accuracy of the clock supplied by the SC1200/SC1201 pro-
cessor is 50 PPM.
4.5.6
The Video processor requires the following clock sources:
Dot
The Dot clock is generated by PLL2. It is supplied to the
Display Controller in the GX1 module (DCLK) that creates
the pixel information, and is returned to the Graphics block
(PCLK) with this information. PLL2 uses the 27 MHz clock
to generate the Dot clock.
Video
The Video clock source depends on the source of the video
data.
• If the video data is coming from the GX1 module
• If the video data is coming directly from the VIP block
(Capture Video mode), the video clock is generated by
the Display Controller.
(Direct Video mode), the Video Clock is generated by
the VIP block.
AMD Geode™ SC1200/SC1201 Processor Data Book
Video Processor Clocks
General Configuration Block