SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 201

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0
AMD Geode™ SC1200/SC1201 Processor Data Book
Index 73h
Index 74h-75h
Index 76h
This register is used in conjunction with F0 Index 74h (IOCS0# Base Address register).
Index 77h
Index 78h-7Bh
Index 7Ch-7Fh
This register is used in conjunction with F0 Index 78h (DOCCS# Base Address register).
Table 6-29. F0: PCI Header/Bridge Configuration Registers for GPIO and LPC Support (Continued)
31:27
15:0
31:0
Bit
4:0
4:0
26
6
5
7
6
5
Description
Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 70h; range configured in bits [4:0]) cause IOCS1# to be asserted.
0: Disable.
1: Enable.
IOCS1# I/O Address Range. This 5-bit field is used to select the range of IOCS1#.
00000: 1 Byte
00001: 2 Bytes
00011: 4 Bytes
00111: 8 Bytes
I/O Chip Select 0 Base Address. This 16-bit value represents the I/O base address used to enable the assertion of
IOCS0# (ball A10 - see PMR[23] in Table 4-2 on page 72).
This register is used in conjunction with F0 Index 76h (IOCS0# Control register).
I/O Chip Select 0 Positive Decode (IOCS0#).
0: Disable.
1: Enable.
Writes Result in Chip Select. When this bit is set to 1, writes to configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
Reads Result in Chip Select. When this bit is set to 1, reads from configured I/O address (base address configured in F0
Index 74h; range configured in bits [4:0]) cause IOCS0# to be asserted.
0: Disable.
1: Enable.
IOCS0# I/O Address Range. This 5-bit field is used to select the range of IOCS0#.
00000: 1 Byte
00001: 2 Bytes
00011: 4 Bytes
00111: 8 Bytes
DiskOnChip Chip Select Base Address. This 32-bit value represents the memory base address used to enable assertion
of DOCCS# (ball A9 or N31, see PMR[23] in Table 4-2 on page 72).
This register is used in conjunction with F0 Index 7Ch (DOCCS# Control register).
Reserved. Must be set to 0.
DiskOnChip Chip Select Positive Decode (DOCCS#).
0: Disable.
1: Enable.
DOCCS# Base Address Register (R/W)
IOCS0# Base Address Register (R/W)
DOCCS# Control Register (R/W)
IOCS0# Control Register (R/W)
01111: 16 Bytes
11111: 32 Bytes
All other combinations are reserved.
01111: 16 Bytes
11111: 32 Bytes
All other combinations are reserved.
Reserved
Reserved
32579B
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 0000h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
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