SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 261

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Core Logic Module - IDE Controller Registers - Function 2
AMD Geode™ SC1200/SC1201 Processor Data Book
Offset 08h
Offset 09h
Offset 0Ah
Offset 0Bh
Offset 0Ch-0Fh
31:2
Bit
7:4
2:1
4:3
1:0
3
0
7
6
5
2
1
0
Table 6-36. F2BAR4+I/O Offset: IDE Controller Configuration Registers (Continued)
Description
Reserved. Must be set to 0. Must return 0 on reads.
Read or Write Control. Sets the direction of bus master transfers.
0: PCI reads are performed.
1: PCI writes are performed.
This bit should not be changed when the bus master is active.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Control. Controls the state of the bus master.
0: Disable master.
1: Enable master.
Bus master operations can be halted by setting this bit to 0. Once an operation has been halted, it cannot be resumed. If this
bit is set to 0 while a bus master operation is active, the command is aborted and the data transferred from the drive is dis-
carded. This bit should be reset after completion of data transfer.
Reserved. (Read Only)
Drive 1 DMA Capable. Allow Drive 1 to perform DMA transfers.
0: Disable.
1: Enable.
Drive 0 DMA Capable. Allow Drive 0 to perform DMA transfers.
0: Disable.
1: Enable.
Reserved. Must be set to 0. Must return 0 on reads.
Bus Master Interrupt. Indicates if the bus master detected an interrupt.
0: No.
1: Yes. Write 1 to clear.
Bus Master Error. Indicates if the bus master detected an error during data transfer.
0: No.
1: Yes. Write 1 to clear.
Bus Master Active. Indicates if the bus master is active.
0: No.
1: Yes.
Pointer to the Physical Region Descriptor Table. This bit field contains a PRD table pointer for IDE Bus Master 1.
When written, this field points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register bit 0
= 1), it loads the pointer and updates this field (by adding 08h) so that is points to the next PRD.
When read, this register points to the next PRD.
Reserved. Must be set to 0.
IDE Bus Master 1 Command Register — Secondary (R/W)
IDE Bus Master 1 PRD Table Address — Secondary (R/W)
IDE Bus Master 1 Status Register — Secondary (R/W)
Not Used
Not Used
32579B
Reset Value: 00000000h
Reset Value: 00h
Reset Value: 00h
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