SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 51

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Signal Definitions
3.4.2
3.4.3
AMD Geode™ SC1200/SC1201 Processor Data Book
Signal Name
DQM7
DQM6
DQM5
DQM4
DQM3
DQM2
DQM1
DQM0
CKEA
SDCLK3
SDCLK2
SDCLK1
SDCLK0
SDCLK_IN
SDCLK_OUT
Signal Name
VPD7
VPD6
VPD5
VPD4
VPD3
VPD2
VPD1
VPD0
VPCKIN
Memory Interface Signals (Continued)
Video Port Interface Signals
Ball No.
Ball No.
AB31
AG29
AK21
AC31
AG30
AH23
AA28
AK28
AL15
AL11
AL22
AJ21
AJ27
W29
V29
G31
H28
H29
H30
H31
F31
J28
J29
J30
Type
Type
O
O
O
O
I
I
I
Description
Data Mask Control Bits. During memory read cycles,
these outputs control whether SDRAM output buffers are
driven on the MD bus or not. All DQM signals are
asserted during read cycles.
During memory write cycles, these outputs control
whether or not MD data is written into SDRAM.
DQM[7:0] connect directly to the [DQM7:0] pins of each
DIMM connector.
Clock Enable. These signals are used to enter Suspend/
power-down mode. CKEA is used with CS[1:0]#.
If CKEA goes low when no read or write cycle is in
progress, the SDRAM enters power-down mode. To
ensure that SDRAM data remains valid, the self-refresh
command is executed. To exit this mode, and return to
normal operation, drive CKEA high.
These signals should have an external pull-down resistor
of 33 KΩ.
SDRAM Clocks. SDRAM uses these clocks to sample
all control, address, and data lines. To ensure that the
Suspend mode functions correctly, SDCLK3 and
SDCLK1 should be used with CS1#. SDCLK2 and
SDCLK0 should be used together with CS0#.
SDRAM Clock Input. The SC1200/SC1201 processor
samples the memory read data on this clock. Works in
conjunction with the SDCLK_OUT signal.
SDRAM Clock Output. This output is routed back to
SDCLK_IN. The board designer should vary the length of
the board trace to control skew between SDCLK_IN and
SDCLK.
Description
Video Port Data. The data is input from the CCIR-656
video decoder.
Video Port Clock Input. The clock input from the video
decoder.
32579B
Mux
Mux
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