SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 98

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

5.4.2
As described in Section 5.3.2 "Banked Logical Device Reg-
isters" on page 92, each functional block is associated with
a Logical Device Number (LDN). This section provides the
register descriptions for each LDN.
The register descriptions in this subsection use the follow-
ing abbreviations for Type:
• R/W
• R
• W
• RO
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit
1.
98
Index
F0h
F1h
F2h
F3h
30h
60h
61h
62h
63h
70h
71h
74h
75h
The logical device registers are maintained, and all RTC mechanisms are functional.
Logical Device Control and Configuration
= Read/Write
= Read from a specific address returns the
= Write
= Read Only
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
value of a specific register. Write to the
same address is to a different register.
clears it to 0. Writing 0 has no effect.
32579B
Configuration Register or Action
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.
Standard Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.
Standard Base Address LSB register. Bit 0 (for A0) is RO, 0b.
Extended Base Address MSB register. Bits [7:3] (for A[15:11]) are RO, 00000b.
Extended Base Address LSB register. Bit 0 (for A0) is RO, 0b.
Interrupt Number.
Interrupt Type. Bit 1 is R/W; other bits are RO.
Report no DMA assignment.
Report no DMA assignment.
RAM Lock register (RLR).
Date of Month Alarm Offset register (DOMAO). Sets index of Date of Month Alarm
register in the standard base address.
Month Alarm Offset register (MONAO). Sets index of Month Alarm register in the
standard base address.
Century Offset register (CENO). Sets index of Century register in the standard base
address.
Table 5-6. Relevant RTC Configuration Registers
5.4.2.1
Table 5-6 lists the registers which are relevant to configura-
tion of the Real-Time Clock (RTC). Only the last registers
(F0h-F3h) are described here (Table 5-7). See Table 5-3
"Standard Configuration Registers" on page 95 for descrip-
tions of the other registers.
AMD Geode™ SC1200/SC1201 Processor Data Book
LDN 00h - Real-Time Clock
SuperI/O Module
1
Reset
Value
00h
00h
70h
00h
72h
08h
00h
04h
04h
00h
00h
00h
00h