SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 87

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

General Configuration Block
4.5.7
The clock generator and PLL registers are described in Table 4-8.
AMD Geode™ SC1200/SC1201 Processor Data Book
Offset 10h
This register holds the maximum core clock multiplier value. The maximum clock frequency allowed by the core, is the Fast-PCI clock
multiplied by this value.
Offset 11h
Offset 12h
This register controls operation of the PLLs.
Offset 13h-17h
Offset 18h-1Bh
31:24
23:19
18:8
Bit
7:4
3:0
5:0
7
6
5
4
3
2
1
0
7
6
Clock Registers
Description
Reserved.
MCM (Maximum Clock Multiplier). This 4-bit value is the maximum multiplier value allowed for the core clock generator. It
is derived from strap pins CLKSEL[3:0] based on the multiplier value in Table 4-7 on page 85.
Reserved.
EXPCID (Disable External PCI Clock).
0: External PCI clock is enabled.
1: External PCI clock is disabled.
GPD (Disable Graphic Pixel Reference Clock).
0: PLL2 input clock is enabled.
1: PLL2 input clock is disabled.
Reserved.
PLL3SD (Shut Down PLL3). AC97 codec clock.
0: PLL3 is enabled.
1: PLL3 is shutdown.
FM1SD (Shut Down PLL4).
0: PLL4 is enabled.
1: PLL4 is shutdown, unless internal Fast-PCI clock is strapped to 48 MHz.
C48MD (Disable SuperI/O and USB Clock).
0: USB and SuperI/O clock is enabled.
1: USB and SuperI/O clock is disabled.
Reserved. Write as read.
MFFC (MFF Counter Value).
Fvco
OSCCLK = 27 MHz
Reserved. Write as read.
MFBC (MFB Counter Value).
Fvco
OSCCLK = 27 MHz
Note:
Reserved. Write as read.
Reserved. Must be set to 0.
MOC (MO Counter Value).
Fvco
OSCCLK = 27 MHz
Bits 18, 9, and 8 cannot be changed. Bit 18 is always a 1; bits 9 and 8 are always 0.
= OSCCLK * MFBC / (MFFC * MOC)
= OSCCLK * MFBC / (MFFC * MOC)
= OSCCLK * MFBC / (MFFC * MOC)
Maximum Core Clock Multiplier Register - MCCM (RO)
Table 4-8. Clock Generator Configuration
PLL3 Configuration Register - PLL3C (R/W)
PLL Power Control Register - PPCR (R/W)
Reserved - RSVD
Reserved - RSVD
32579B
Reset Value: Strapped Value
Reset Value: E1040005h
Reset Value: 2Fh
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