SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 175

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Core Logic Module - PCI Configuration Space and Access
6.3
The Core Logic module is a multi-function module. Its reg-
ister space can be broadly divided into three categories in
which specific types of registers are located:
1)
2)
3)
The following subsections provide:
• A brief discussion on how to access the registers
• Core Logic module register summaries.
• Bit formats for Core Logic module registers.
AMD Geode™ SC1200/SC1201 Processor Data Book
Function 0 (F0): Bridge Configuration, GPIO and LPC Configuration Register Space
Function 1 (F1): SMI Status and ACPI Timer Configuration Register Space
Function 2 (F2): IDE Controller Configuration Register Space
Function 3 (F3): Audio Configuration Register Space
Function 4 (F4): Video Processor Configuration Register Space
Function 5 (F5): X-Bus Expansion Configuration Register Space
PCIUSB: USB Controller Configuration Register Space
Note:
Space Mapping
Configuration
located in PCI Configuration Space.
1 (Enable)
Chipset Register Space (F0-F5) (Note that F4 is for
Video Processor support, see Section 7.3.1 on page
333 for register descriptions): Comprised of six sepa-
rate functions, each with its own register space, con-
sisting of PCI header registers and configuration
registers.
The PCI header is a 256-byte region used for configur-
ing a PCI device or function. The first 64 bytes are the
same for all PCI devices and are predefined by the
PCI specification. These registers are used to config-
ure the PCI for the device. The rest of the 256-byte
region is used to configure the device or function itself.
USB Controller Register Space (PCIUSB): Consists of
the standard PCI header registers. The USB controller
supports three ports and is OpenHCI compliant.
ISA Legacy Register Space (I/O Ports): Contains all
the legacy compatibility I/O ports that are internal,
trapped, shadowed, or snooped.
31
The device number depends upon the IDSEL Strap Override bit (F5BAR0+I/O Offset 04h[0]). This bit allows selection of the
address lines to be used as the IDSEL. By Default: IDSEL = AD28 (1001 0) for F0-F5, AD29 (1001 1) for PCIUSB.
Register Descriptions
80h
80h
80h
80h
80h
80h
80h
30
Reserved
000 000
Table 6-13. PCI Configuration Address Register (0CF8h)
24
23
Bus Number
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
16
15
1001 0 or 1000 0
1001 0 or 1000 0
1001 0 or 1000 0
1001 0 or 1000 0
1001 0 or 1000 0
1001 0 or 1000 0
1001 1 or 1000 1
Device Number
xxxx x (Note)
6.3.1
Configuration cycles are generated in the processor. All
configuration registers in the Core Logic module are
accessed through the PCI interface using the PCI Type
One Configuration Mechanism. This mechanism uses two
DWORD I/O locations at 0CF8h and 0CFCh. The first loca-
tion (0CF8h) references the Configuration Address register.
The second location (0CFCh) references the Configuration
Data Register (CDR).
To access PCI configuration space, write the Configuration
Address (0CF8h) Register with data that specifies the Core
Logic module as the device on PCI being accessed, along
with the configuration register offset. On the following
cycle, a read or write to the Configuration Data Register
(CDR) causes a PCI configuration cycle to the Core Logic
module. Byte, WORD, or DWORD accesses are allowed to
CDR at 0CFCh, 0CFDh, 0CFEh, or 0CFFh.
The Core Logic module has seven PCI configuration regis-
ter sets, one for each function (F0-F5) and USB (PCIUSB).
Base Address Registers (BARx) in F0-F5 and PCIUSB set
the base addresses for additional I/O or memory mapped
configuration registers for each function.
Table 6-13 shows the PCI Configuration Address Register
(0CF8h) and how to access the PCI header registers.
11
10
PCI Configuration Space and Access
Methods
Function
000
001
010
011
100
101
000
xxx
8
7
32579B
xxxx xx
Index
Index
Index
Index
Index
Index
Index
Index
2
1
00 (Always)
DWORD
00
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0