SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 31

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Signal Definitions
AMD Geode™ SC1200/SC1201 Processor Data Book
Ball
No.
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
6,2
GPIO19
Signal Name
AD26
D2
AD24
D0
V
AD25
D1
GNT0#
DID0
GNT1#
DID1
V
ROMCS#
BOOT16
INTC#
IOCHRDY
V
IRTX
SOUT3
V
AV
AV
AV
AV
SLCT
TFTD15
F_C/BE3#
PD4
TFTD10
F_AD4
IO
IO
IO
SSCRT
CCCRT
SSCRT
SSCRT
SSPLL2
Table 3-2.
(PU/PD)
(PU
(PU
(PU
(PD
(PD
(PD
PWR
PWR
PWR
PWR
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
22.5
22.5
22.5
100
100
100
)
)
)
)
)
)
Buffer
IN
IN
IN
O
O
IN
IN
IN
IN
IN
IN
IN
Type
IN
O
O
O
O
O
O
O
O
O
O
IN
O
O
O
O
O
BGU481 Ball Assignment - Sorted by Ball Number (Continued)
IN
IN
14/14
14/14
STRP
STRP
STRP
---
---
---
---
---
---
---
---
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
TS1
3/5
TS
3/5
8/8
8/8
1/4
1/4
1/4
TS
T
T
,
,
,
,
,
,
,
,
1
Power
Rail
V
V
V
V
V
V
V
V
V
V
V
---
---
---
---
---
---
---
---
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Configuration
Cycle Multiplexed
Cycle Multiplexed
---
Cycle Multiplexed
---
Strap (See Table 3-
4 on page 44.)
---
Strap (See Table 3-
4 on page 44.)
---
---
Strap (See Table 3-
4 on page 44.)
PMR[9] = 0 and
PMR[4] = 0
PMR[9] = 0 and
PMR[4] = 1
PMR[9] = 1 and
PMR[4] = 1
---
PMR[6] = 0
PMR[6] = 1
---
---
---
---
---
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
3
3
3
3
3
3
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
Ball
No.
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
6,2
6,2
6,2
Signal Name
PD5
TFTD11
F_AD5
PD3
TFTD9
F_AD3
PD0
TFTD6
VOPD5
F_AD0
V
SVC
Cr
Cb
TVB
TVR
TVREF
V
INTB#
AV
GPIO9
DCD2#
IDE_IOW1#
SDTEST2
V
IO
IO
IO
SSUSB
(PU/PD)
(PU
(PU
(PU
(PU
(PU
PWR
PWR
PWR
GND
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
22.5
22.5
22.5
22.5
22.5
)
)
)
)
)
32579B
Buffer
O
O
O
O
O
O
WIRE
WIRE
Type
IN
IN
IN
O
O
O
O
O
O
O
IN
IN
IN
14/14
14/14
14/14
14/14
14/14
14/14
---
---
---
---
1/4
1/4
1/4
1/4
PCI
TS
1/4
1/4
2/5
TS
T
T
T
,
,
,
,
1
AV
AV
Power
Rail
V
V
V
V
V
---
CCTV
CCTV
---
---
---
IO
IO
IO
IO
IO
Configuration
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
PMR[23]
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]
PMR[15] = 0) and
(PMR[27] = 0 and
FPCI_MON = 0)
(PMR[23]
PMR[15] = 1) and
(PMR[27] = 0 and
FPCI_MON = 0)
PMR[23]
(PMR[27] = 1 or
FPCI_MON = 1)
---
See F4BAR0+
Memory Offset
C08h[4:3] bit
description on
page 356.
---
---
---
---
PMR[18] = 0 and
PMR[8] = 0
PMR[18] = 1 and
PMR[8] = 0
PMR[18] = 0 and
PMR[8] = 1
PMR[18] = 1 and
PMR[8] = 1
---
3
3
3
3
3
3
3
3
3
3
= 0 and
= 1 and
= 0 and
= 0 and
= 1 and
= 0 and
= 0 and
= 0 and
= 1 and
= 1 and
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