SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 287

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Core Logic Module - USB Controller Registers - PCIUSB
AMD Geode™ SC1200/SC1201 Processor Data Book
Offset 10h-13h
Note:
Offset 14h-17h
29:7
29:7
Bit
31
30
31
30
6
5
4
3
2
1
0
6
5
4
3
Writing a 1 to a bit in this register sets the corresponding bit, while writing a 0 leaves the bit unchanged.
Description
MasterInterruptEnable. This bit is a global interrupt enable. A write of 1 allows interrupts to be enabled via the specific
enable bits listed above.
OwnershipChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Ownership Change.
Reserved. Read/Write 0s.
RootHubStatusChangeEnable.
0: Ignore.
1: Enable interrupt generation due to Root Hub Status Change.
FrameNumberOverflowEnable.
0: Ignore.
1: Enable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable. This event is not implemented. All writes to this bit are ignored.
ResumeDetectedEnable.
0: Ignore.
1: Enable interrupt generation due to Resume Detected.
StartOfFrameEnable.
0: Ignore.
1: Enable interrupt generation due to Start of Frame.
WritebackDoneHeadEnable.
0: Ignore.
1: Enable interrupt generation due to Writeback Done Head.
SchedulingOverrunEnable.
0: Ignore.
1: Enable interrupt generation due to Scheduling Overrun.
MasterInterruptEnable. Global interrupt disable. A write of 1 disables all interrupts.
OwnershipChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Ownership Change.
Reserved. Read/Write 0s.
RootHubStatusChangeEnable.
0: Ignore.
1: Disable interrupt generation due to Root Hub Status Change.
FrameNumberOverflowEnable.
0: Ignore.
1: Disable interrupt generation due to Frame Number Overflow.
UnrecoverableErrorEnable. This event is not implemented. All writes to this bit will be ignored.
ResumeDetectedEnable.
0: Ignore.
1: Disable interrupt generation due to Resume Detected.
Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
HcInterruptDisable Register (R/W)
HcInterruptEnable Register (R/W)
32579B
Reset Value = 00000000h
Reset Value = 00000000h
287