SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 331

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Video Processor Module
The TV interface consists of a set of four DACs.
• Normally, two DACs drive the composite TV output, and
• In SCART mode, three DACS drive TVR, TVG, and TVB
Each TV DAC has a resolution of 10-bits, and is capable of
running at a clock rate of up to 30 MHz. These DACs can
generate voltage levels from 0 to 1.3V, when driving 75Ω
double terminated loads.
7.2.7
The TFT interface can be programmed to one of two sets of
balls: IDE balls or Parallel Port balls. PMR[23] of the Gen-
eral Configuration registers program where the TFT inter-
face exists (see Table 4-2 on page 72).
Note: If the TFT interface is on the IDE balls, the maxi-
Support for a TFT panel requires power sequencing and an
18-bit (6-bit RGB), digital output. The relevant digital output
signals are available from the SC1200/SC1201 processor.
AMD Geode™ SC1200/SC1201 Processor Data Book
FP_PWR_EN
FP_VDD_ON
two other DACs drive S-Video TV output.
signals, and the fourth DAC drives the composite signal.
HSYNC, VSYNC,
TFTDE, TFTDCK
mum FPCLK supported is 40 MHz. If the TFT inter-
face is on the Parallel Port balls the maximum
FPCLK supported is 80 MHz.
TFTD[17:0],
TFT Interface
bit
T
0
T
1
Figure 7-15. TFT Power Sequence
TFT output signals are:
• TFTD[5:0] for blue signals
• TFTD[11:6] for green signals
• TFTD[17:12] for red signals
• HSYNC and VSYNC - sync signals
• TFTDCK - data clock signal.
• TFTDE - data enable signal.
• FP_VDD_ON - power control signal
Power Sequence
Power sequence is used to control assertion of
FP_VDD_ON and TFTD signals.
All bits related to power sequence configuration are located
in the Display Configuration register (F4BAR0+Memory
Offset 04h).
After enabling CRT_EN (bit 0), and FP_PWR_EN (bit 6),
the state machine waits until the next VSYNC to switch on
the FP_VDD_ON signal. The state machine then asserts
the TFTD[17:0] signals after the delay programmed via
PWR_SEQ_DLY (bits [19:17]) When FP_PWR_EN (bit 6)
is set to 0, the reverse sequence happens for powering
down the TFT.
T
T
0
1
is time to next VSYNC
is a programmable multiple of frame time
T
0
+T
1
32579B
T
1
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