SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 352

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

352
Offset 424h-427h
Offset 428h-43Bh
Offset 43Ch-43Fh
Offset 800h-803h
This register is updated at each occurrence of HSYNC.
Offset 804h-807h
This register is updated at each occurrence of HSYNC.
Offset 808h-80Bh
This register is updated at each occurrence of VSYNC.
31:21
31:16
31:28
27:16
15:12
31:28
27:16
15:12
31:28
27:26
25:24
23:22
21:12
11:10
20:0
15:0
11:0
11:0
Bit
9:0
1
0
Table 7-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
CT_GENLOCK_EN (Enable Continuous GenLock Function).
0: The continuous GenLock function is disabled.
1: Enable locking (i.e., synchronization) of the GX1 VSYNC with the VIP VSYNC on every VSYNC (i.e., continuous lock-
Note:
SG_GENLOCK_EN (Enable a Single GenLock Function).
0: GenLock is disabled if bit 1 (CT_GENLOCK_EN) = 0.
1: Enable synchronization (i.e., locking) of GX1 VSYNC with the VIP VSYNC and synchronization of the TV encoder field
Note:
Reserved.
GENLOCK_DEL (GenLock Delay). Indicates the delay (in 27 MHz clocks) between the VIP VSYNC and the GX1 module’s
Display Controller VSYNC.
CGENTO1 (Even Field Continuous GenLock Timeout).
CGENTO0 (Odd Field Continuous GenLock Timeout).
Reserved.
H_DISP_START (Horizontal Display Start). Specifies the first horizontal valid pixel position on a TV screen, in pixel clocks.
Reserved.
H_TOTAL (Horizontal Total). Specifies the total number of pixels per line - 1, for TV. For NTSC, use 857; for PAL use 863.
Reserved.
H_SYNC_END (Horizontal Sync End). Specifies the horizontal synchronization end position in pixel clocks.
Reserved.
H_SYNC_START (Horizontal Sync Start). Specifies the horizontal synchronization start position in pixel clocks.
Reserved.
V_DISP_SKEW_EVEN (Vertical Display Skew). Specifies the vertical display end skew in terms of horizontal lines for all
even fields. Recommended value is 1.
V_DISP_SKEW_ODD (Vertical Display Skew). Specifies the vertical display start skew in terms of horizontal lines for all
odd fields. Recommended value is 1.
Reserved.
V_SYNC_END (Vertical Sync End). Specifies the vertical synchronization end position in terms of horizontal lines.
Reserved.
VSYNC_START (Vertical Sync Start). Specifies the vertical synchronization start position in terms of horizontal lines.
ing).
with the VIP field, once. During the synchronization process, the TV encoder field is determined by bit 5 of this register.
When in Direct Video mode, it is critical that the field of the TV encoder and the Video Input Port (F4BAR2+Memory Off-
set 08h[24]) be the same after the synchronization event. After locking once, this bit is reset by hardware to 0.
If bit 0 (SG_GENLOCK_EN) = 1, it overrides the value of this bit.
If this bit = 1, it overrides the value of bit 1 (CT_GENLOCK_EN).
32579B
Continuous GenLock Timeout Register (R/W)
Horizontal Sync Timing Register (R/W)
Vertical Sync Timing Register (R/W)
Horizontal Timing Register (R/W)
GenLock Delay Register (R/W)
Reserved
Video Processor Module - Video Processor Registers - Function 4
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: 1FFF1FFFh
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h