SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 256

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

6.4.3
The register space designated as Function 2 (F2) is used
to configure Channels 0 and 1 and the PCI portion of sup-
port hardware for the IDE controllers. The bit formats for
the PCI Header/Channels 0 and 1 Registers are given in
Table 6-35.
256
Index 00h-01h
Index 02h-03h
Index 04h-05h
Index 06h-07h
Index 08h
Index 09h-0Bh
Index 0Ch
Index 0Dh
Index 0Eh
Index 0Fh
Index 10h-13h
Reserved. Reserved for possible future use by the Core Logic module.
Index 14h-17h
Reserved. Reserved for possible future use by the Core Logic module.
Index 18h-1Bh
Reserved. Reserved for possible future use by the Core Logic module.
Index 1Ch-1Fh
Reserved. Reserved for possible future use by the Core Logic module.
Index 20h-23h
Base Address 0 Register. This register allows access to I/O mapped Bus Mastering IDE registers. Bits [3:0] are read only (0001), indi-
cating a 16-byte I/O address range. Refer to Table 6-36 on page 260 for the IDE controller register bit formats and reset values.
Index 24h-2Bh
Index 2Ch-2Dh
Index 2Eh-2Fh
15:3
31:4
Bit
3:0
2
1
0
Table 6-35. F2: PCI Header/Channels 0 and 1 Registers for IDE Controller Configuration
IDE Controller Registers - Function 2
Description
Reserved. (Read Only)
Bus Master. Allow the Core Logic module bus mastering capabilities.
0: Disable.
1: Enable. (Default)
This bit must be set to 1.
Reserved. (Read Only)
I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus.
0: Disable.
1: Enable.
This bit must be enabled, in order to access I/O offsets through F2BAR4 (for more information see F2 Index 20h).
Bus Mastering IDE Base Address.
Address Range. (Read Only)
32579B
Base Address Register 4 - F2BAR4 (R/W)
Base Address Register 0 - F2BAR0 (RO)
Base Address Register 1 - F2BAR1 (RO)
Base Address Register 2 - F2BAR2 (RO)
Base Address Register 3 - F2BAR3 (RO)
Vendor Identification Register (RO)
Device Identification Register (RO)
PCI Cache Line Size Register (RO)
Device Revision ID Register (RO)
PCI Latency Timer Register (RO)
PCI Class Code Register (RO)
PCI Command Register (R/W)
Subsystem Vendor ID (RO)
PCI Status Register (RO)
PCI BIST Register (RO)
PCI Header Type (RO)
Subsystem ID (RO)
Reserved
Located in the PCI Header Registers of F2 is a Base
Address Register (F2BAR4) used for pointing to the regis-
ter space designated for support of the IDE controllers,
described later in this section.
Core Logic Module - IDE Controller Registers - Function 2
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000001h
Reset Value: 010180h
Reset Value: 100Bh
Reset Value: 100Bh
Reset Value: 0502h
Reset Value: 0000h
Reset Value: 0280h
Reset Value: 0502h
Reset Value: 01h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h