SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 350

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

350
Offset 404h-407h
Offset 408h-40Bh
Offset 40Ch-40Fh
Offset 410h-413h
31:30
29:25
31:30
29:25
27:4
31:0
24:2
24:2
Bit
1:0
1:0
1:0
30
29
28
3
2
Table 7-9. F4BAR0+Memory Offset: Video Processor Configuration Registers (Continued)
Description
Video FIFO OverFlow (Full).
0: No overflow has occurred.
1: Overflow has occurred.
Write 1 to reset this bit.
VBI FIFO Underflow (Empty).
0: No underflow has occurred.
1: Underflow has occurred.
Write 1 to reset this bit.
VBI FIFO Overflow (Full).
0: No overflow has occurred.
1: Overflow has occurred.
Write 1 to reset this bit.
Reserved. Set to 0.
Upscale horizontally VBI data by 2.
0: No upscale. VBI data pass through.
1: Upscale horizontally by 2.
VBI_SOURCE (VBI Source). Selects the VBI source.
0: VIP block.
1: GX1 module.
Note:
VID_SEL (Video Select). Selects the source of the video data.
00: GX1 module.
10: VIP block.
01: Reserved.
11: Reserved.
The GX1 module’s video clock must be active at all times, regardless of the source of video input.
Reserved.
Reserved.
LINE_OFFSET_ODD (Odd Field Line Offset). Specifies the offset (in number of lines) of line 2 from VSYNC.
VBI_LINE_EN_ODD (VBI Odd Field Line Enable). Bits [24:2] enable VBI lines 24 to 2 respectively for odd fields.
0: Disable.
1: Enable.
Bit 24 controls active video line. If bit 24 is set, all active video lines are treated as VBI lines.
Reserved.
Reserved.
LINE_OFFSET_EVEN (Even Field Line Offset). Specifies the offset (in number of lines) of line 2 from VSYNC.
VBI_LINE_EN_EVEN (VBI Even Field Line Enable). Bits [24:2] enable VBI lines 24 to 2 respectively for even fields.
0: Disable.
1: Enable.
Bit 24 controls active video line. If bit 24 is set, all active video lines are treated as VBI lines.
Reserved.
VBI is enabled by setting one or more of the VBI (odd/even) line-enable register bits. (Odd lines enabled at
F4BAR0+Memory Offset 40Ch[24:2]; even lines enabled at F4BAR0+Memory Offset 410h[24:2].)
32579B
Video Processor Test Mode Register (R/W)
VBI Line Enable Register - Even (R/W)
VBI Line Enable Register - Odd (R/W)
Reserved
Video Processor Module - Video Processor Registers - Function 4
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00000000h