SC1200UFH-266 AMD (ADVANCED MICRO DEVICES), SC1200UFH-266 Datasheet - Page 18

• Manufacturer Part Number: SC1200UFH-266
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of SC1200UFH-266

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

18
GX_BASE+ 8400h-8403h
GX_BASE+
Memory Offset
8400h-8403h
8404h-8407h
8408h-840Bh
840Ch-840Fh
8414h-8417h
8418h-841Bh
841Ch-841Fh
31:30
28:27
25:24
23:22
20:18
16:8
Bit
7:6
29
26
21
17
5
Description
MDCTL (MD[63:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
MABACTL (MA[12:0] and BA[1:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
MEMCTL (RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength). 11 is strongest, 00 is weakest.
RSVD (Reserved). Write as 0.
RSVD (Reserved). Must be written as 0. Wait state on the X-Bus x_data during read cycles - for debug only.
SDCLKRATE (SDRAM Clock Ratio). Selects SDRAM clock ratio.
000: Reserved
001: ÷ 2
010: ÷ 2.5
011: ÷ 3 (Default)
Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.
SDCLKSTRT (Start SDCLK). Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of this reg-
ister).
0: Clear.
1: Enable.
This bit must transition from zero (written to zero) to one (written to one) in order to start SDCLK or to change the shift value.
RFSHRATE (Refresh Interval). This field determines the number of processor core clocks multiplied by 64 between refresh
cycles to the DRAM. By default, the refresh interval is 00h. Refresh is turned off by default.
RFSHSTAG (Refresh Staggering). This field determines number of clocks between the RFSH commands to each of the
four banks during refresh cycles:
00: 0 SDRAM clocks
01: 1 SDRAM clocks (Default)
10: 2 SDRAM clocks
11: 4 SDRAM clocks
Staggering is used to help reduce power spikes during refresh by refreshing one bank at a time. If only one bank is installed,
this field must be written as 00.
2CLKADDR (Two Clock Address Setup). Assert memory address for one extra clock before CS# is asserted.
0: Disable.
1: Enable.
This can be used to compensate for address setup at high frequencies and/or high loads.
Table 2-1. SC1200/SC1201 Processor Memory Controller Register Summary
Table 2-2. SC1200/SC1201 Processor Memory Controller Registers
Width
(Bits)
32579B
32
32
32
32
32
32
32
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name/Function
MC_MEM_CNTRL1. Memory Controller Control Register 1
MC_MEM_CNTRL2. Memory Controller Control Register 2
MC_BANK_CFG. Memory Controller Bank Configuration
MC_SYNC_TIM1. Memory Controller Synchronous Timing
Register 1
MC_GBASE_ADD. Memory Controller Graphics Base
Address Register
MC_DR_ADD. Memory Controller Dirty RAM Address
Register
MC_DR_ACC. Memory Controller Dirty RAM Access
Register
MC_MEM_CNTRL1 (R/W)
100: ÷ 3.5
101: ÷ 4
110: ÷ 4.5
111: ÷ 5
AMD Geode™ SC1200/SC1201 Processor Data Book
Reset Value: 248C0040h
Architecture Overview
Reset Value
248C0040h
2A733225h
00000801h
41104110h
00000000h
00000000h
0000000xh